cpu.h (6e040755f12eba34d2fa3d56b18de32d63fea631) cpu.h (cbc3a6a4cc675516328a2b0d3602355d68b6302d)
1#ifndef SPARC_CPU_H
2#define SPARC_CPU_H
3
4#include "qemu-common.h"
5#include "qemu/bswap.h"
6#include "cpu-qom.h"
7
8#define ALIGNED_ONLY

--- 501 unchanged lines hidden (view full) ---

510 uint32_t pstate;
511 uint32_t tl;
512 uint32_t maxtl;
513 uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
514 uint64_t agregs[8]; /* alternate general registers */
515 uint64_t bgregs[8]; /* backup for normal global registers */
516 uint64_t igregs[8]; /* interrupt general registers */
517 uint64_t mgregs[8]; /* mmu general registers */
1#ifndef SPARC_CPU_H
2#define SPARC_CPU_H
3
4#include "qemu-common.h"
5#include "qemu/bswap.h"
6#include "cpu-qom.h"
7
8#define ALIGNED_ONLY

--- 501 unchanged lines hidden (view full) ---

510 uint32_t pstate;
511 uint32_t tl;
512 uint32_t maxtl;
513 uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
514 uint64_t agregs[8]; /* alternate general registers */
515 uint64_t bgregs[8]; /* backup for normal global registers */
516 uint64_t igregs[8]; /* interrupt general registers */
517 uint64_t mgregs[8]; /* mmu general registers */
518 uint64_t glregs[8 * MAXTL_MAX];
518 uint64_t fprs;
519 uint64_t tick_cmpr, stick_cmpr;
520 CPUTimer *tick, *stick;
521#define TICK_NPT_MASK 0x8000000000000000ULL
522#define TICK_INT_DIS 0x8000000000000000ULL
523 uint64_t gsr;
524 uint32_t gl; // UA2005
525 /* UA 2005 hyperprivileged registers */

--- 84 unchanged lines hidden (view full) ---

610void cpu_put_psr(CPUSPARCState *env1, target_ulong val);
611void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val);
612#ifdef TARGET_SPARC64
613target_ulong cpu_get_ccr(CPUSPARCState *env1);
614void cpu_put_ccr(CPUSPARCState *env1, target_ulong val);
615target_ulong cpu_get_cwp64(CPUSPARCState *env1);
616void cpu_put_cwp64(CPUSPARCState *env1, int cwp);
617void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate);
519 uint64_t fprs;
520 uint64_t tick_cmpr, stick_cmpr;
521 CPUTimer *tick, *stick;
522#define TICK_NPT_MASK 0x8000000000000000ULL
523#define TICK_INT_DIS 0x8000000000000000ULL
524 uint64_t gsr;
525 uint32_t gl; // UA2005
526 /* UA 2005 hyperprivileged registers */

--- 84 unchanged lines hidden (view full) ---

611void cpu_put_psr(CPUSPARCState *env1, target_ulong val);
612void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val);
613#ifdef TARGET_SPARC64
614target_ulong cpu_get_ccr(CPUSPARCState *env1);
615void cpu_put_ccr(CPUSPARCState *env1, target_ulong val);
616target_ulong cpu_get_cwp64(CPUSPARCState *env1);
617void cpu_put_cwp64(CPUSPARCState *env1, int cwp);
618void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate);
619void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl);
618#endif
619int cpu_cwp_inc(CPUSPARCState *env1, int cwp);
620int cpu_cwp_dec(CPUSPARCState *env1, int cwp);
621void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
622
623/* int_helper.c */
624void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno);
625

--- 204 unchanged lines hidden --- 		620#endif
621int cpu_cwp_inc(CPUSPARCState *env1, int cwp);
622int cpu_cwp_dec(CPUSPARCState *env1, int cwp);
623void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
624
625/* int_helper.c */
626void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno);
627

--- 204 unchanged lines hidden ---