translate.c (7c9f70386d1aae67055a9a278880cde6c278217c) translate.c (e5d8053e76bda79744710e5b59e70f9fcbce7df7)
1/*
2 * SH4 translation
3 *
4 * Copyright (c) 2005 Samuel Tardieu
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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326 }
327
328 tcg_gen_brcondi_i32(TCG_COND_NE, ds, 0, l1);
329 gen_goto_tb(ctx, 1, ctx->pc + 2);
330 gen_set_label(l1);
331 gen_jump(ctx);
332}
333
1/*
2 * SH4 translation
3 *
4 * Copyright (c) 2005 Samuel Tardieu
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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326 }
327
328 tcg_gen_brcondi_i32(TCG_COND_NE, ds, 0, l1);
329 gen_goto_tb(ctx, 1, ctx->pc + 2);
330 gen_set_label(l1);
331 gen_jump(ctx);
332}
333
334static inline void gen_load_fpr64(TCGv_i64 t, int reg)
334static inline void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
335{
336 tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]);
337}
338
335{
336 tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]);
337}
338
339static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
339static inline void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
340{
341 tcg_gen_extr_i64_i32(cpu_fregs[reg + 1], cpu_fregs[reg], t);
342}
343
344#define B3_0 (ctx->opcode & 0xf)
345#define B6_4 ((ctx->opcode >> 4) & 0x7)
346#define B7_4 ((ctx->opcode >> 4) & 0xf)
347#define B7_0 (ctx->opcode & 0xff)

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973 return;
974 case 0x200a: /* xor Rm,Rn */
975 tcg_gen_xor_i32(REG(B11_8), REG(B11_8), REG(B7_4));
976 return;
977 case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
978 CHECK_FPU_ENABLED
979 if (ctx->tbflags & FPSCR_SZ) {
980 TCGv_i64 fp = tcg_temp_new_i64();
340{
341 tcg_gen_extr_i64_i32(cpu_fregs[reg + 1], cpu_fregs[reg], t);
342}
343
344#define B3_0 (ctx->opcode & 0xf)
345#define B6_4 ((ctx->opcode >> 4) & 0x7)
346#define B7_4 ((ctx->opcode >> 4) & 0xf)
347#define B7_0 (ctx->opcode & 0xff)

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973 return;
974 case 0x200a: /* xor Rm,Rn */
975 tcg_gen_xor_i32(REG(B11_8), REG(B11_8), REG(B7_4));
976 return;
977 case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
978 CHECK_FPU_ENABLED
979 if (ctx->tbflags & FPSCR_SZ) {
980 TCGv_i64 fp = tcg_temp_new_i64();
981 gen_load_fpr64(fp, XHACK(B7_4));
982 gen_store_fpr64(fp, XHACK(B11_8));
981 gen_load_fpr64(ctx, fp, XHACK(B7_4));
982 gen_store_fpr64(ctx, fp, XHACK(B11_8));
983 tcg_temp_free_i64(fp);
984 } else {
985 tcg_gen_mov_i32(FREG(B11_8), FREG(B7_4));
986 }
987 return;
988 case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
989 CHECK_FPU_ENABLED
990 if (ctx->tbflags & FPSCR_SZ) {

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1083 CHECK_FPU_ENABLED
1084 if (ctx->tbflags & FPSCR_PR) {
1085 TCGv_i64 fp0, fp1;
1086
1087 if (ctx->opcode & 0x0110)
1088 break; /* illegal instruction */
1089 fp0 = tcg_temp_new_i64();
1090 fp1 = tcg_temp_new_i64();
983 tcg_temp_free_i64(fp);
984 } else {
985 tcg_gen_mov_i32(FREG(B11_8), FREG(B7_4));
986 }
987 return;
988 case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
989 CHECK_FPU_ENABLED
990 if (ctx->tbflags & FPSCR_SZ) {

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1083 CHECK_FPU_ENABLED
1084 if (ctx->tbflags & FPSCR_PR) {
1085 TCGv_i64 fp0, fp1;
1086
1087 if (ctx->opcode & 0x0110)
1088 break; /* illegal instruction */
1089 fp0 = tcg_temp_new_i64();
1090 fp1 = tcg_temp_new_i64();
1091 gen_load_fpr64(fp0, DREG(B11_8));
1092 gen_load_fpr64(fp1, DREG(B7_4));
1091 gen_load_fpr64(ctx, fp0, DREG(B11_8));
1092 gen_load_fpr64(ctx, fp1, DREG(B7_4));
1093 switch (ctx->opcode & 0xf00f) {
1094 case 0xf000: /* fadd Rm,Rn */
1095 gen_helper_fadd_DT(fp0, cpu_env, fp0, fp1);
1096 break;
1097 case 0xf001: /* fsub Rm,Rn */
1098 gen_helper_fsub_DT(fp0, cpu_env, fp0, fp1);
1099 break;
1100 case 0xf002: /* fmul Rm,Rn */

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1105 break;
1106 case 0xf004: /* fcmp/eq Rm,Rn */
1107 gen_helper_fcmp_eq_DT(cpu_sr_t, cpu_env, fp0, fp1);
1108 return;
1109 case 0xf005: /* fcmp/gt Rm,Rn */
1110 gen_helper_fcmp_gt_DT(cpu_sr_t, cpu_env, fp0, fp1);
1111 return;
1112 }
1093 switch (ctx->opcode & 0xf00f) {
1094 case 0xf000: /* fadd Rm,Rn */
1095 gen_helper_fadd_DT(fp0, cpu_env, fp0, fp1);
1096 break;
1097 case 0xf001: /* fsub Rm,Rn */
1098 gen_helper_fsub_DT(fp0, cpu_env, fp0, fp1);
1099 break;
1100 case 0xf002: /* fmul Rm,Rn */

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1105 break;
1106 case 0xf004: /* fcmp/eq Rm,Rn */
1107 gen_helper_fcmp_eq_DT(cpu_sr_t, cpu_env, fp0, fp1);
1108 return;
1109 case 0xf005: /* fcmp/gt Rm,Rn */
1110 gen_helper_fcmp_gt_DT(cpu_sr_t, cpu_env, fp0, fp1);
1111 return;
1112 }
1113 gen_store_fpr64(fp0, DREG(B11_8));
1113 gen_store_fpr64(ctx, fp0, DREG(B11_8));
1114 tcg_temp_free_i64(fp0);
1115 tcg_temp_free_i64(fp1);
1116 } else {
1117 switch (ctx->opcode & 0xf00f) {
1118 case 0xf000: /* fadd Rm,Rn */
1119 gen_helper_fadd_FT(FREG(B11_8), cpu_env,
1120 FREG(B11_8), FREG(B7_4));
1121 break;

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1684 case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */
1685 CHECK_FPU_ENABLED
1686 if (ctx->tbflags & FPSCR_PR) {
1687 TCGv_i64 fp;
1688 if (ctx->opcode & 0x0100)
1689 break; /* illegal instruction */
1690 fp = tcg_temp_new_i64();
1691 gen_helper_float_DT(fp, cpu_env, cpu_fpul);
1114 tcg_temp_free_i64(fp0);
1115 tcg_temp_free_i64(fp1);
1116 } else {
1117 switch (ctx->opcode & 0xf00f) {
1118 case 0xf000: /* fadd Rm,Rn */
1119 gen_helper_fadd_FT(FREG(B11_8), cpu_env,
1120 FREG(B11_8), FREG(B7_4));
1121 break;

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1684 case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */
1685 CHECK_FPU_ENABLED
1686 if (ctx->tbflags & FPSCR_PR) {
1687 TCGv_i64 fp;
1688 if (ctx->opcode & 0x0100)
1689 break; /* illegal instruction */
1690 fp = tcg_temp_new_i64();
1691 gen_helper_float_DT(fp, cpu_env, cpu_fpul);
1692 gen_store_fpr64(fp, DREG(B11_8));
1692 gen_store_fpr64(ctx, fp, DREG(B11_8));
1693 tcg_temp_free_i64(fp);
1694 }
1695 else {
1696 gen_helper_float_FT(FREG(B11_8), cpu_env, cpu_fpul);
1697 }
1698 return;
1699 case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1700 CHECK_FPU_ENABLED
1701 if (ctx->tbflags & FPSCR_PR) {
1702 TCGv_i64 fp;
1703 if (ctx->opcode & 0x0100)
1704 break; /* illegal instruction */
1705 fp = tcg_temp_new_i64();
1693 tcg_temp_free_i64(fp);
1694 }
1695 else {
1696 gen_helper_float_FT(FREG(B11_8), cpu_env, cpu_fpul);
1697 }
1698 return;
1699 case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1700 CHECK_FPU_ENABLED
1701 if (ctx->tbflags & FPSCR_PR) {
1702 TCGv_i64 fp;
1703 if (ctx->opcode & 0x0100)
1704 break; /* illegal instruction */
1705 fp = tcg_temp_new_i64();
1706 gen_load_fpr64(fp, DREG(B11_8));
1706 gen_load_fpr64(ctx, fp, DREG(B11_8));
1707 gen_helper_ftrc_DT(cpu_fpul, cpu_env, fp);
1708 tcg_temp_free_i64(fp);
1709 }
1710 else {
1711 gen_helper_ftrc_FT(cpu_fpul, cpu_env, FREG(B11_8));
1712 }
1713 return;
1714 case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */

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1720 tcg_gen_andi_i32(FREG(B11_8), FREG(B11_8), 0x7fffffff);
1721 return;
1722 case 0xf06d: /* fsqrt FRn */
1723 CHECK_FPU_ENABLED
1724 if (ctx->tbflags & FPSCR_PR) {
1725 if (ctx->opcode & 0x0100)
1726 break; /* illegal instruction */
1727 TCGv_i64 fp = tcg_temp_new_i64();
1707 gen_helper_ftrc_DT(cpu_fpul, cpu_env, fp);
1708 tcg_temp_free_i64(fp);
1709 }
1710 else {
1711 gen_helper_ftrc_FT(cpu_fpul, cpu_env, FREG(B11_8));
1712 }
1713 return;
1714 case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */

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1720 tcg_gen_andi_i32(FREG(B11_8), FREG(B11_8), 0x7fffffff);
1721 return;
1722 case 0xf06d: /* fsqrt FRn */
1723 CHECK_FPU_ENABLED
1724 if (ctx->tbflags & FPSCR_PR) {
1725 if (ctx->opcode & 0x0100)
1726 break; /* illegal instruction */
1727 TCGv_i64 fp = tcg_temp_new_i64();
1728 gen_load_fpr64(fp, DREG(B11_8));
1728 gen_load_fpr64(ctx, fp, DREG(B11_8));
1729 gen_helper_fsqrt_DT(fp, cpu_env, fp);
1729 gen_helper_fsqrt_DT(fp, cpu_env, fp);
1730 gen_store_fpr64(fp, DREG(B11_8));
1730 gen_store_fpr64(ctx, fp, DREG(B11_8));
1731 tcg_temp_free_i64(fp);
1732 } else {
1733 gen_helper_fsqrt_FT(FREG(B11_8), cpu_env, FREG(B11_8));
1734 }
1735 return;
1736 case 0xf07d: /* fsrra FRn */
1737 CHECK_FPU_ENABLED
1738 break;

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1748 tcg_gen_movi_i32(FREG(B11_8), 0x3f800000);
1749 }
1750 return;
1751 case 0xf0ad: /* fcnvsd FPUL,DRn */
1752 CHECK_FPU_ENABLED
1753 {
1754 TCGv_i64 fp = tcg_temp_new_i64();
1755 gen_helper_fcnvsd_FT_DT(fp, cpu_env, cpu_fpul);
1731 tcg_temp_free_i64(fp);
1732 } else {
1733 gen_helper_fsqrt_FT(FREG(B11_8), cpu_env, FREG(B11_8));
1734 }
1735 return;
1736 case 0xf07d: /* fsrra FRn */
1737 CHECK_FPU_ENABLED
1738 break;

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1748 tcg_gen_movi_i32(FREG(B11_8), 0x3f800000);
1749 }
1750 return;
1751 case 0xf0ad: /* fcnvsd FPUL,DRn */
1752 CHECK_FPU_ENABLED
1753 {
1754 TCGv_i64 fp = tcg_temp_new_i64();
1755 gen_helper_fcnvsd_FT_DT(fp, cpu_env, cpu_fpul);
1756 gen_store_fpr64(fp, DREG(B11_8));
1756 gen_store_fpr64(ctx, fp, DREG(B11_8));
1757 tcg_temp_free_i64(fp);
1758 }
1759 return;
1760 case 0xf0bd: /* fcnvds DRn,FPUL */
1761 CHECK_FPU_ENABLED
1762 {
1763 TCGv_i64 fp = tcg_temp_new_i64();
1757 tcg_temp_free_i64(fp);
1758 }
1759 return;
1760 case 0xf0bd: /* fcnvds DRn,FPUL */
1761 CHECK_FPU_ENABLED
1762 {
1763 TCGv_i64 fp = tcg_temp_new_i64();
1764 gen_load_fpr64(fp, DREG(B11_8));
1764 gen_load_fpr64(ctx, fp, DREG(B11_8));
1765 gen_helper_fcnvds_DT_FT(cpu_fpul, cpu_env, fp);
1766 tcg_temp_free_i64(fp);
1767 }
1768 return;
1769 case 0xf0ed: /* fipr FVm,FVn */
1770 CHECK_FPU_ENABLED
1771 if ((ctx->tbflags & FPSCR_PR) == 0) {
1772 TCGv m, n;

--- 571 unchanged lines hidden --- 		1765 gen_helper_fcnvds_DT_FT(cpu_fpul, cpu_env, fp);
1766 tcg_temp_free_i64(fp);
1767 }
1768 return;
1769 case 0xf0ed: /* fipr FVm,FVn */
1770 CHECK_FPU_ENABLED
1771 if ((ctx->tbflags & FPSCR_PR) == 0) {
1772 TCGv m, n;

--- 571 unchanged lines hidden ---