cpu.h (d8276573da58e8ce78dab8c46dd660efd664bcb7) cpu.h (74433bf083b0766aba81534f92de13194f23ff3e)
1/*
2 * SH4 emulation
3 *
4 * Copyright (c) 2005 Samuel Tardieu
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef SH4_CPU_H
21#define SH4_CPU_H
22
23#include "qemu-common.h"
24#include "cpu-qom.h"
1/*
2 * SH4 emulation
3 *
4 * Copyright (c) 2005 Samuel Tardieu
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef SH4_CPU_H
21#define SH4_CPU_H
22
23#include "qemu-common.h"
24#include "cpu-qom.h"
25#include "exec/cpu-defs.h"
25
26
26#define TARGET_LONG_BITS 32
27#define ALIGNED_ONLY
28
29/* CPU Subtypes */
30#define SH_CPU_SH7750 (1 << 0)
31#define SH_CPU_SH7750S (1 << 1)
32#define SH_CPU_SH7750R (1 << 2)
33#define SH_CPU_SH7751 (1 << 3)
34#define SH_CPU_SH7751R (1 << 4)
35#define SH_CPU_SH7785 (1 << 5)
36#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
37#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
38
39#define CPUArchState struct CPUSH4State
40
27#define ALIGNED_ONLY
28
29/* CPU Subtypes */
30#define SH_CPU_SH7750 (1 << 0)
31#define SH_CPU_SH7750S (1 << 1)
32#define SH_CPU_SH7750R (1 << 2)
33#define SH_CPU_SH7751 (1 << 3)
34#define SH_CPU_SH7751R (1 << 4)
35#define SH_CPU_SH7785 (1 << 5)
36#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
37#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
38
39#define CPUArchState struct CPUSH4State
40
41#include "exec/cpu-defs.h"
42
43#define TARGET_PAGE_BITS 12 /* 4k XXXXX */
44
45#define TARGET_PHYS_ADDR_SPACE_BITS 32
46#ifdef CONFIG_USER_ONLY
47# define TARGET_VIRT_ADDR_SPACE_BITS 31
48#else
49# define TARGET_VIRT_ADDR_SPACE_BITS 32
50#endif
51
52#define SR_MD 30
53#define SR_RB 29
54#define SR_BL 28
55#define SR_FD 15
56#define SR_M 9
57#define SR_Q 8
58#define SR_I3 7
59#define SR_I2 6

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127 uint8_t wt:1; /* write through */
128 uint8_t sa:3; /* space attribute (PCMCIA) */
129 uint8_t tc:1; /* timing control */
130} tlb_t;
131
132#define UTLB_SIZE 64
133#define ITLB_SIZE 4
134
41#define SR_MD 30
42#define SR_RB 29
43#define SR_BL 28
44#define SR_FD 15
45#define SR_M 9
46#define SR_Q 8
47#define SR_I3 7
48#define SR_I2 6

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116 uint8_t wt:1; /* write through */
117 uint8_t sa:3; /* space attribute (PCMCIA) */
118 uint8_t tc:1; /* timing control */
119} tlb_t;
120
121#define UTLB_SIZE 64
122#define ITLB_SIZE 4
123
135#define NB_MMU_MODES 2
136#define TARGET_INSN_START_EXTRA_WORDS 1
137
138enum sh_features {
139 SH_FEATURE_SH4A = 1,
140 SH_FEATURE_BCR3_AND_BCR4 = 2,
141};
142
143typedef struct memory_content {

--- 274 unchanged lines hidden --- 		124#define TARGET_INSN_START_EXTRA_WORDS 1
125
126enum sh_features {
127 SH_FEATURE_SH4A = 1,
128 SH_FEATURE_BCR3_AND_BCR4 = 2,
129};
130
131typedef struct memory_content {

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