cpu.h (61462af65af0d2f56b56097b9ac5eb32f471a673) cpu.h (e1933d1435d1d0ace7c93bdc429f7e4f0c499e92)
1/*
2 * SH4 emulation
3 *
4 * Copyright (c) 2005 Samuel Tardieu
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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91#define FPSCR_RM_NEAREST (0 << 0)
92#define FPSCR_RM_ZERO (1 << 0)
93
94#define DELAY_SLOT_MASK 0x7
95#define DELAY_SLOT (1 << 0)
96#define DELAY_SLOT_CONDITIONAL (1 << 1)
97#define DELAY_SLOT_RTE (1 << 2)
98
1/*
2 * SH4 emulation
3 *
4 * Copyright (c) 2005 Samuel Tardieu
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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91#define FPSCR_RM_NEAREST (0 << 0)
92#define FPSCR_RM_ZERO (1 << 0)
93
94#define DELAY_SLOT_MASK 0x7
95#define DELAY_SLOT (1 << 0)
96#define DELAY_SLOT_CONDITIONAL (1 << 1)
97#define DELAY_SLOT_RTE (1 << 2)
98
99#define TB_FLAG_ENVFLAGS_MASK DELAY_SLOT_MASK
100
99typedef struct tlb_t {
100 uint32_t vpn; /* virtual page number */
101 uint32_t ppn; /* physical page number */
102 uint32_t size; /* mapped page size in bytes */
103 uint8_t asid; /* address space identifier */
104 uint8_t v:1; /* validity */
105 uint8_t sz:2; /* page size */
106 uint8_t sh:1; /* share status */

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383 env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T));
384}
385
386static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
387 target_ulong *cs_base, uint32_t *flags)
388{
389 *pc = env->pc;
390 *cs_base = 0;
101typedef struct tlb_t {
102 uint32_t vpn; /* virtual page number */
103 uint32_t ppn; /* physical page number */
104 uint32_t size; /* mapped page size in bytes */
105 uint8_t asid; /* address space identifier */
106 uint8_t v:1; /* validity */
107 uint8_t sz:2; /* page size */
108 uint8_t sh:1; /* share status */

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385 env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T));
386}
387
388static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
389 target_ulong *cs_base, uint32_t *flags)
390{
391 *pc = env->pc;
392 *cs_base = 0;
391 *flags = (env->flags & DELAY_SLOT_MASK) /* Bits 0- 2 */
393 *flags = (env->flags & TB_FLAG_ENVFLAGS_MASK) /* Bits 0-2 */
392 | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */
393 | (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-30 */
394 | (env->sr & (1u << SR_FD)) /* Bit 15 */
395 | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
396}
397
398#endif /* SH4_CPU_H */
394 | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */
395 | (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-30 */
396 | (env->sr & (1u << SR_FD)) /* Bit 15 */
397 | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
398}
399
400#endif /* SH4_CPU_H */