translate.c (61d56494884b0d4bbf78d0561258b3548dea3390) translate.c (e91a7227cb802ea62ffa14707ebc2f588b01213d)
1/*
2 * RISC-V emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.

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50 EXT_ZERO,
51} DisasExtend;
52
53typedef struct DisasContext {
54 DisasContextBase base;
55 /* pc_succ_insn points to the instruction following base.pc_next */
56 target_ulong pc_succ_insn;
57 target_ulong priv_ver;
1/*
2 * RISC-V emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.

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50 EXT_ZERO,
51} DisasExtend;
52
53typedef struct DisasContext {
54 DisasContextBase base;
55 /* pc_succ_insn points to the instruction following base.pc_next */
56 target_ulong pc_succ_insn;
57 target_ulong priv_ver;
58 target_ulong misa;
58 RISCVMXL xl;
59 uint32_t misa_ext;
59 uint32_t opcode;
60 uint32_t mstatus_fs;
61 uint32_t mstatus_hs_fs;
62 uint32_t mem_idx;
63 /* Remember the rounding mode encoded in the previous fp instruction,
64 which we have already installed into env->fp_status. Or -1 for
65 no previous fp instruction. Note that we exit the TB when writing
66 to any system register, which includes CSR_FRM, so we do not have

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81 CPUState *cs;
82 TCGv zero;
83 /* Space for 3 operands plus 1 extra for address computation. */
84 TCGv temp[4];
85} DisasContext;
86
87static inline bool has_ext(DisasContext *ctx, uint32_t ext)
88{
60 uint32_t opcode;
61 uint32_t mstatus_fs;
62 uint32_t mstatus_hs_fs;
63 uint32_t mem_idx;
64 /* Remember the rounding mode encoded in the previous fp instruction,
65 which we have already installed into env->fp_status. Or -1 for
66 no previous fp instruction. Note that we exit the TB when writing
67 to any system register, which includes CSR_FRM, so we do not have

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82 CPUState *cs;
83 TCGv zero;
84 /* Space for 3 operands plus 1 extra for address computation. */
85 TCGv temp[4];
86} DisasContext;
87
88static inline bool has_ext(DisasContext *ctx, uint32_t ext)
89{
89 return ctx->misa & ext;
90 return ctx->misa_ext & ext;
90}
91
92#ifdef TARGET_RISCV32
93# define is_32bit(ctx) true
94#elif defined(CONFIG_USER_ONLY)
95# define is_32bit(ctx) false
96#else
97static inline bool is_32bit(DisasContext *ctx)
98{
91}
92
93#ifdef TARGET_RISCV32
94# define is_32bit(ctx) true
95#elif defined(CONFIG_USER_ONLY)
96# define is_32bit(ctx) false
97#else
98static inline bool is_32bit(DisasContext *ctx)
99{
99 return (ctx->misa & RV32) == RV32;
100 return ctx->xl == MXL_RV32;
100}
101#endif
102
103/* The word size for this operation. */
104static inline int oper_len(DisasContext *ctx)
105{
106 return ctx->w ? 32 : TARGET_LONG_BITS;
107}

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508 if (riscv_has_ext(env, RVH)) {
509 ctx->virt_enabled = riscv_cpu_virt_enabled(env);
510 } else {
511 ctx->virt_enabled = false;
512 }
513#else
514 ctx->virt_enabled = false;
515#endif
101}
102#endif
103
104/* The word size for this operation. */
105static inline int oper_len(DisasContext *ctx)
106{
107 return ctx->w ? 32 : TARGET_LONG_BITS;
108}

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509 if (riscv_has_ext(env, RVH)) {
510 ctx->virt_enabled = riscv_cpu_virt_enabled(env);
511 } else {
512 ctx->virt_enabled = false;
513 }
514#else
515 ctx->virt_enabled = false;
516#endif
516 ctx->misa = env->misa;
517 ctx->xl = env->misa_mxl;
518 ctx->misa_ext = env->misa_ext;
517 ctx->frm = -1; /* unknown rounding mode */
518 ctx->ext_ifencei = cpu->cfg.ext_ifencei;
519 ctx->vlen = cpu->cfg.vlen;
520 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
521 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
522 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
523 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
524 ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);

--- 120 unchanged lines hidden --- 		519 ctx->frm = -1; /* unknown rounding mode */
520 ctx->ext_ifencei = cpu->cfg.ext_ifencei;
521 ctx->vlen = cpu->cfg.vlen;
522 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
523 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
524 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
525 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
526 ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);

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