machine.c (3e9f48bcdabe57f8f90cf19f01bbbf3c86937267) machine.c (e91a7227cb802ea62ffa14707ebc2f588b01213d)
1/*
2 * RISC-V VMState Description
3 *
4 * Copyright (c) 2020 Huawei Technologies Co., Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.

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135 VMSTATE_UINT64(env.mstatus_hs, RISCVCPU),
136
137 VMSTATE_END_OF_LIST()
138 }
139};
140
141const VMStateDescription vmstate_riscv_cpu = {
142 .name = "cpu",
1/*
2 * RISC-V VMState Description
3 *
4 * Copyright (c) 2020 Huawei Technologies Co., Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.

--- 126 unchanged lines hidden (view full) ---

135 VMSTATE_UINT64(env.mstatus_hs, RISCVCPU),
136
137 VMSTATE_END_OF_LIST()
138 }
139};
140
141const VMStateDescription vmstate_riscv_cpu = {
142 .name = "cpu",
143 .version_id = 2,
144 .minimum_version_id = 2,
143 .version_id = 3,
144 .minimum_version_id = 3,
145 .fields = (VMStateField[]) {
146 VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
147 VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
148 VMSTATE_UINTTL(env.pc, RISCVCPU),
149 VMSTATE_UINTTL(env.load_res, RISCVCPU),
150 VMSTATE_UINTTL(env.load_val, RISCVCPU),
151 VMSTATE_UINTTL(env.frm, RISCVCPU),
152 VMSTATE_UINTTL(env.badaddr, RISCVCPU),
153 VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
154 VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
155 VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
145 .fields = (VMStateField[]) {
146 VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
147 VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
148 VMSTATE_UINTTL(env.pc, RISCVCPU),
149 VMSTATE_UINTTL(env.load_res, RISCVCPU),
150 VMSTATE_UINTTL(env.load_val, RISCVCPU),
151 VMSTATE_UINTTL(env.frm, RISCVCPU),
152 VMSTATE_UINTTL(env.badaddr, RISCVCPU),
153 VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
154 VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
155 VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
156 VMSTATE_UINTTL(env.misa, RISCVCPU),
157 VMSTATE_UINTTL(env.misa_mask, RISCVCPU),
156 VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
157 VMSTATE_UINT32(env.misa_ext, RISCVCPU),
158 VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
159 VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
158 VMSTATE_UINT32(env.features, RISCVCPU),
159 VMSTATE_UINTTL(env.priv, RISCVCPU),
160 VMSTATE_UINTTL(env.virt, RISCVCPU),
161 VMSTATE_UINTTL(env.resetvec, RISCVCPU),
162 VMSTATE_UINTTL(env.mhartid, RISCVCPU),
163 VMSTATE_UINT64(env.mstatus, RISCVCPU),
164 VMSTATE_UINTTL(env.mip, RISCVCPU),
165 VMSTATE_UINT32(env.miclaim, RISCVCPU),

--- 29 unchanged lines hidden --- 		160 VMSTATE_UINT32(env.features, RISCVCPU),
161 VMSTATE_UINTTL(env.priv, RISCVCPU),
162 VMSTATE_UINTTL(env.virt, RISCVCPU),
163 VMSTATE_UINTTL(env.resetvec, RISCVCPU),
164 VMSTATE_UINTTL(env.mhartid, RISCVCPU),
165 VMSTATE_UINT64(env.mstatus, RISCVCPU),
166 VMSTATE_UINTTL(env.mip, RISCVCPU),
167 VMSTATE_UINT32(env.miclaim, RISCVCPU),

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