| gdbstub.c (e3955ae93f5151ad2e982440b7c8d3776a9afee2) | gdbstub.c (e91a7227cb802ea62ffa14707ebc2f588b01213d) |
|---|---|
| 1/* 2 * RISC-V GDB Server Stub 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. --- 40 unchanged lines hidden (view full) --- 49 return sizeof(target_ulong); 50 } 51 return 0; 52} 53 54static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n) 55{ 56 if (n < 32) { | 1/* 2 * RISC-V GDB Server Stub 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. --- 40 unchanged lines hidden (view full) --- 49 return sizeof(target_ulong); 50 } 51 return 0; 52} 53 54static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n) 55{ 56 if (n < 32) { |
| 57 if (env->misa & RVD) { | 57 if (env->misa_ext & RVD) { |
| 58 return gdb_get_reg64(buf, env->fpr[n]); 59 } | 58 return gdb_get_reg64(buf, env->fpr[n]); 59 } |
| 60 if (env->misa & RVF) { | 60 if (env->misa_ext & RVF) { |
| 61 return gdb_get_reg32(buf, env->fpr[n]); 62 } 63 /* there is hole between ft11 and fflags in fpu.xml */ 64 } else if (n < 36 && n > 32) { 65 target_ulong val = 0; 66 int result; 67 /* 68 * CSR_FFLAGS is at index 1 in csr_register, and gdb says it is FP --- 117 unchanged lines hidden (view full) --- 186 cpu->dyn_csr_xml = g_string_free(s, false); 187 return CSR_TABLE_SIZE; 188} 189 190void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) 191{ 192 RISCVCPU *cpu = RISCV_CPU(cs); 193 CPURISCVState *env = &cpu->env; | 61 return gdb_get_reg32(buf, env->fpr[n]); 62 } 63 /* there is hole between ft11 and fflags in fpu.xml */ 64 } else if (n < 36 && n > 32) { 65 target_ulong val = 0; 66 int result; 67 /* 68 * CSR_FFLAGS is at index 1 in csr_register, and gdb says it is FP --- 117 unchanged lines hidden (view full) --- 186 cpu->dyn_csr_xml = g_string_free(s, false); 187 return CSR_TABLE_SIZE; 188} 189 190void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) 191{ 192 RISCVCPU *cpu = RISCV_CPU(cs); 193 CPURISCVState *env = &cpu->env; |
| 194 if (env->misa & RVD) { | 194 if (env->misa_ext & RVD) { |
| 195 gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 196 36, "riscv-64bit-fpu.xml", 0); | 195 gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 196 36, "riscv-64bit-fpu.xml", 0); |
| 197 } else if (env->misa & RVF) { | 197 } else if (env->misa_ext & RVF) { |
| 198 gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 199 36, "riscv-32bit-fpu.xml", 0); 200 } 201#if defined(TARGET_RISCV32) 202 gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, 203 1, "riscv-32bit-virtual.xml", 0); 204#elif defined(TARGET_RISCV64) 205 gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, 206 1, "riscv-64bit-virtual.xml", 0); 207#endif 208 209 gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, 210 riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_regs), 211 "riscv-csr.xml", 0); 212} | 198 gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 199 36, "riscv-32bit-fpu.xml", 0); 200 } 201#if defined(TARGET_RISCV32) 202 gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, 203 1, "riscv-32bit-virtual.xml", 0); 204#elif defined(TARGET_RISCV64) 205 gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, 206 1, "riscv-64bit-virtual.xml", 0); 207#endif 208 209 gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, 210 riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_regs), 211 "riscv-csr.xml", 0); 212} |