gdbstub.c (33a24910aedaa184515b04921cc8a5dcccd99235) gdbstub.c (ac1e86710000ba3cf2e80836fb3f66ba12b169b8)
1/*
2 * RISC-V GDB Server Stub
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.

--- 297 unchanged lines hidden (view full) ---

306
307void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
308{
309 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
310 RISCVCPU *cpu = RISCV_CPU(cs);
311 CPURISCVState *env = &cpu->env;
312 if (env->misa_ext & RVD) {
313 gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
1/*
2 * RISC-V GDB Server Stub
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.

--- 297 unchanged lines hidden (view full) ---

306
307void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
308{
309 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
310 RISCVCPU *cpu = RISCV_CPU(cs);
311 CPURISCVState *env = &cpu->env;
312 if (env->misa_ext & RVD) {
313 gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
314 32, "riscv-64bit-fpu.xml", 0);
314 gdb_find_static_feature("riscv-64bit-fpu.xml"),
315 0);
315 } else if (env->misa_ext & RVF) {
316 gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
316 } else if (env->misa_ext & RVF) {
317 gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
317 32, "riscv-32bit-fpu.xml", 0);
318 gdb_find_static_feature("riscv-32bit-fpu.xml"),
319 0);
318 }
319 if (env->misa_ext & RVV) {
320 gdb_register_coprocessor(cs, riscv_gdb_get_vector,
321 riscv_gdb_set_vector,
320 }
321 if (env->misa_ext & RVV) {
322 gdb_register_coprocessor(cs, riscv_gdb_get_vector,
323 riscv_gdb_set_vector,
322 ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs)->num_regs,
323 "riscv-vector.xml", 0);
324 ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
325 0);
324 }
325 switch (mcc->misa_mxl_max) {
326 case MXL_RV32:
327 gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
328 riscv_gdb_set_virtual,
326 }
327 switch (mcc->misa_mxl_max) {
328 case MXL_RV32:
329 gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
330 riscv_gdb_set_virtual,
329 1, "riscv-32bit-virtual.xml", 0);
331 gdb_find_static_feature("riscv-32bit-virtual.xml"),
332 0);
330 break;
331 case MXL_RV64:
332 case MXL_RV128:
333 gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
334 riscv_gdb_set_virtual,
333 break;
334 case MXL_RV64:
335 case MXL_RV128:
336 gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
337 riscv_gdb_set_virtual,
335 1, "riscv-64bit-virtual.xml", 0);
338 gdb_find_static_feature("riscv-64bit-virtual.xml"),
339 0);
336 break;
337 default:
338 g_assert_not_reached();
339 }
340
341 if (cpu->cfg.ext_zicsr) {
342 gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
340 break;
341 default:
342 g_assert_not_reached();
343 }
344
345 if (cpu->cfg.ext_zicsr) {
346 gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
343 riscv_gen_dynamic_csr_feature(cs, cs->gdb_num_regs)->num_regs,
344 "riscv-csr.xml", 0);
347 riscv_gen_dynamic_csr_feature(cs, cs->gdb_num_regs),
348 0);
345 }
346}
349 }
350}