debug.h (a42bd0016654cafd6ca8ca4dbb82fc921ca19ae4) debug.h (9d5a84db91f12bd843206a57e0cde01e6a9d488d)
1/*
2 * QEMU RISC-V Native Debug Support
3 *
4 * Copyright (c) 2022 Wind River Systems, Inc.
5 *
6 * Author:
7 * Bin Meng <bin.meng@windriver.com>
8 *

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51 struct CPUWatchpoint *wp;
52} type2_trigger_t;
53
54/* tdata1 field masks */
55
56#define RV32_TYPE(t) ((uint32_t)(t) << 28)
57#define RV32_TYPE_MASK (0xf << 28)
58#define RV32_DMODE BIT(27)
1/*
2 * QEMU RISC-V Native Debug Support
3 *
4 * Copyright (c) 2022 Wind River Systems, Inc.
5 *
6 * Author:
7 * Bin Meng <bin.meng@windriver.com>
8 *

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51 struct CPUWatchpoint *wp;
52} type2_trigger_t;
53
54/* tdata1 field masks */
55
56#define RV32_TYPE(t) ((uint32_t)(t) << 28)
57#define RV32_TYPE_MASK (0xf << 28)
58#define RV32_DMODE BIT(27)
59#define RV32_DATA_MASK 0x7ffffff
59#define RV64_TYPE(t) ((uint64_t)(t) << 60)
60#define RV64_TYPE_MASK (0xfULL << 60)
61#define RV64_DMODE BIT_ULL(59)
60#define RV64_TYPE(t) ((uint64_t)(t) << 60)
61#define RV64_TYPE_MASK (0xfULL << 60)
62#define RV64_DMODE BIT_ULL(59)
63#define RV64_DATA_MASK 0x7ffffffffffffff
62
63/* mcontrol field masks */
64
65#define TYPE2_LOAD BIT(0)
66#define TYPE2_STORE BIT(1)
67#define TYPE2_EXEC BIT(2)
68#define TYPE2_U BIT(3)
69#define TYPE2_S BIT(4)

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65/* mcontrol field masks */
66
67#define TYPE2_LOAD BIT(0)
68#define TYPE2_STORE BIT(1)
69#define TYPE2_EXEC BIT(2)
70#define TYPE2_U BIT(3)
71#define TYPE2_S BIT(4)

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