debug.h (9495c4888a80809ab9dba6d6e536b21c018c77a4) debug.h (31b9798d824512b7daf868cc8581f9a97a9d13a8)
1/*
2 * QEMU RISC-V Native Debug Support
3 *
4 * Copyright (c) 2022 Wind River Systems, Inc.
5 *
6 * Author:
7 * Bin Meng <bin.meng@windriver.com>
8 *

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90bool tdata_available(CPURISCVState *env, int tdata_index);
91
92target_ulong tselect_csr_read(CPURISCVState *env);
93void tselect_csr_write(CPURISCVState *env, target_ulong val);
94
95target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index);
96void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val);
97
1/*
2 * QEMU RISC-V Native Debug Support
3 *
4 * Copyright (c) 2022 Wind River Systems, Inc.
5 *
6 * Author:
7 * Bin Meng <bin.meng@windriver.com>
8 *

--- 81 unchanged lines hidden (view full) ---

90bool tdata_available(CPURISCVState *env, int tdata_index);
91
92target_ulong tselect_csr_read(CPURISCVState *env);
93void tselect_csr_write(CPURISCVState *env, target_ulong val);
94
95target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index);
96void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val);
97
98target_ulong tinfo_csr_read(CPURISCVState *env);
99
98void riscv_cpu_debug_excp_handler(CPUState *cs);
99bool riscv_cpu_debug_check_breakpoint(CPUState *cs);
100bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
101
102void riscv_trigger_init(CPURISCVState *env);
103
104#endif /* RISCV_DEBUG_H */
100void riscv_cpu_debug_excp_handler(CPUState *cs);
101bool riscv_cpu_debug_check_breakpoint(CPUState *cs);
102bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
103
104void riscv_trigger_init(CPURISCVState *env);
105
106#endif /* RISCV_DEBUG_H */