csr.c (2c3e83f92d93fbab071b8a96b8ab769b01902475) csr.c (e91a7227cb802ea62ffa14707ebc2f588b01213d)
1/*
2 * RISC-V Control and Status Registers.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,

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34 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
35}
36
37/* Predicates */
38static RISCVException fs(CPURISCVState *env, int csrno)
39{
40#if !defined(CONFIG_USER_ONLY)
41 /* loose check condition for fcsr in vector extension */
1/*
2 * RISC-V Control and Status Registers.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,

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34 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
35}
36
37/* Predicates */
38static RISCVException fs(CPURISCVState *env, int csrno)
39{
40#if !defined(CONFIG_USER_ONLY)
41 /* loose check condition for fcsr in vector extension */
42 if ((csrno == CSR_FCSR) && (env->misa & RVV)) {
42 if ((csrno == CSR_FCSR) && (env->misa_ext & RVV)) {
43 return RISCV_EXCP_NONE;
44 }
45 if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
46 return RISCV_EXCP_ILLEGAL_INST;
47 }
48#endif
49 return RISCV_EXCP_NONE;
50}
51
52static RISCVException vs(CPURISCVState *env, int csrno)
53{
43 return RISCV_EXCP_NONE;
44 }
45 if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
46 return RISCV_EXCP_ILLEGAL_INST;
47 }
48#endif
49 return RISCV_EXCP_NONE;
50}
51
52static RISCVException vs(CPURISCVState *env, int csrno)
53{
54 if (env->misa & RVV) {
54 if (env->misa_ext & RVV) {
55 return RISCV_EXCP_NONE;
56 }
57 return RISCV_EXCP_ILLEGAL_INST;
58}
59
60static RISCVException ctr(CPURISCVState *env, int csrno)
61{
62#if !defined(CONFIG_USER_ONLY)

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552 env->mstatus = (env->mstatus & ~mask) | (valh & mask);
553
554 return RISCV_EXCP_NONE;
555}
556
557static RISCVException read_misa(CPURISCVState *env, int csrno,
558 target_ulong *val)
559{
55 return RISCV_EXCP_NONE;
56 }
57 return RISCV_EXCP_ILLEGAL_INST;
58}
59
60static RISCVException ctr(CPURISCVState *env, int csrno)
61{
62#if !defined(CONFIG_USER_ONLY)

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552 env->mstatus = (env->mstatus & ~mask) | (valh & mask);
553
554 return RISCV_EXCP_NONE;
555}
556
557static RISCVException read_misa(CPURISCVState *env, int csrno,
558 target_ulong *val)
559{
560 *val = env->misa;
560 target_ulong misa;
561
562 switch (env->misa_mxl) {
563 case MXL_RV32:
564 misa = (target_ulong)MXL_RV32 << 30;
565 break;
566#ifdef TARGET_RISCV64
567 case MXL_RV64:
568 misa = (target_ulong)MXL_RV64 << 62;
569 break;
570#endif
571 default:
572 g_assert_not_reached();
573 }
574
575 *val = misa | env->misa_ext;
561 return RISCV_EXCP_NONE;
562}
563
564static RISCVException write_misa(CPURISCVState *env, int csrno,
565 target_ulong val)
566{
567 if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
568 /* drop write to misa */

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578 /* 'E' excludes all other extensions */
579 if (val & RVE) {
580 /* when we support 'E' we can do "val = RVE;" however
581 * for now we just drop writes if 'E' is present.
582 */
583 return RISCV_EXCP_NONE;
584 }
585
576 return RISCV_EXCP_NONE;
577}
578
579static RISCVException write_misa(CPURISCVState *env, int csrno,
580 target_ulong val)
581{
582 if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
583 /* drop write to misa */

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593 /* 'E' excludes all other extensions */
594 if (val & RVE) {
595 /* when we support 'E' we can do "val = RVE;" however
596 * for now we just drop writes if 'E' is present.
597 */
598 return RISCV_EXCP_NONE;
599 }
600
601 /*
602 * misa.MXL writes are not supported by QEMU.
603 * Drop writes to those bits.
604 */
605
586 /* Mask extensions that are not supported by this hart */
606 /* Mask extensions that are not supported by this hart */
587 val &= env->misa_mask;
607 val &= env->misa_ext_mask;
588
589 /* Mask extensions that are not supported by QEMU */
590 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
591
592 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
593 if ((val & RVD) && !(val & RVF)) {
594 val &= ~RVD;
595 }
596
597 /* Suppress 'C' if next instruction is not aligned
598 * TODO: this should check next_pc
599 */
600 if ((val & RVC) && (GETPC() & ~3) != 0) {
601 val &= ~RVC;
602 }
603
608
609 /* Mask extensions that are not supported by QEMU */
610 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
611
612 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
613 if ((val & RVD) && !(val & RVF)) {
614 val &= ~RVD;
615 }
616
617 /* Suppress 'C' if next instruction is not aligned
618 * TODO: this should check next_pc
619 */
620 if ((val & RVC) && (GETPC() & ~3) != 0) {
621 val &= ~RVC;
622 }
623
604 /* misa.MXL writes are not supported by QEMU */
605 if (riscv_cpu_is_32bit(env)) {
606 val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL);
607 } else {
608 val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL);
624 /* If nothing changed, do nothing. */
625 if (val == env->misa_ext) {
626 return RISCV_EXCP_NONE;
609 }
610
611 /* flush translation cache */
627 }
628
629 /* flush translation cache */
612 if (val != env->misa) {
613 tb_flush(env_cpu(env));
614 }
615
616 env->misa = val;
617
630 tb_flush(env_cpu(env));
631 env->misa_ext = val;
618 return RISCV_EXCP_NONE;
619}
620
621static RISCVException read_medeleg(CPURISCVState *env, int csrno,
622 target_ulong *val)
623{
624 *val = env->medeleg;
625 return RISCV_EXCP_NONE;

--- 1164 unchanged lines hidden --- 		632 return RISCV_EXCP_NONE;
633}
634
635static RISCVException read_medeleg(CPURISCVState *env, int csrno,
636 target_ulong *val)
637{
638 *val = env->medeleg;
639 return RISCV_EXCP_NONE;

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