| cpu_bits.h (513eb437aef7687ad1963d935ffb884fff3c4775) | cpu_bits.h (31b9798d824512b7daf868cc8581f9a97a9d13a8) |
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| 1/* RISC-V ISA constants */ 2 3#ifndef TARGET_RISCV_CPU_BITS_H 4#define TARGET_RISCV_CPU_BITS_H 5 6#define get_field(reg, mask) (((reg) & \ 7 (uint64_t)(mask)) / ((mask) & ~((mask) << 1))) 8#define set_field(reg, mask, val) (((reg) & ~(uint64_t)(mask)) | \ --- 305 unchanged lines hidden (view full) --- 314#define CSR_PMPADDR14 0x3be 315#define CSR_PMPADDR15 0x3bf 316 317/* Debug/Trace Registers (shared with Debug Mode) */ 318#define CSR_TSELECT 0x7a0 319#define CSR_TDATA1 0x7a1 320#define CSR_TDATA2 0x7a2 321#define CSR_TDATA3 0x7a3 | 1/* RISC-V ISA constants */ 2 3#ifndef TARGET_RISCV_CPU_BITS_H 4#define TARGET_RISCV_CPU_BITS_H 5 6#define get_field(reg, mask) (((reg) & \ 7 (uint64_t)(mask)) / ((mask) & ~((mask) << 1))) 8#define set_field(reg, mask, val) (((reg) & ~(uint64_t)(mask)) | \ --- 305 unchanged lines hidden (view full) --- 314#define CSR_PMPADDR14 0x3be 315#define CSR_PMPADDR15 0x3bf 316 317/* Debug/Trace Registers (shared with Debug Mode) */ 318#define CSR_TSELECT 0x7a0 319#define CSR_TDATA1 0x7a1 320#define CSR_TDATA2 0x7a2 321#define CSR_TDATA3 0x7a3 |
| 322#define CSR_TINFO 0x7a4 |
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| 322 323/* Debug Mode Registers */ 324#define CSR_DCSR 0x7b0 325#define CSR_DPC 0x7b1 326#define CSR_DSCRATCH 0x7b2 327 328/* Performance Counters */ 329#define CSR_MHPMCOUNTER3 0xb03 --- 530 unchanged lines hidden --- | 323 324/* Debug Mode Registers */ 325#define CSR_DCSR 0x7b0 326#define CSR_DPC 0x7b1 327#define CSR_DSCRATCH 0x7b2 328 329/* Performance Counters */ 330#define CSR_MHPMCOUNTER3 0xb03 --- 530 unchanged lines hidden --- |