cpu.c (48c1a3e303b5a2cca48679645ad3fbb914db741a) | cpu.c (e124536f37377cff5d68925d4976ad604d0ebf3a) |
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1/* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, --- 604 unchanged lines hidden (view full) --- 613 cc->do_unaligned_access = riscv_cpu_do_unaligned_access; 614 cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; 615 /* For now, mark unmigratable: */ 616 cc->vmsd = &vmstate_riscv_cpu; 617#endif 618 cc->gdb_arch_name = riscv_gdb_arch_name; 619 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 620 cc->tcg_ops.initialize = riscv_translate_init; | 1/* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, --- 604 unchanged lines hidden (view full) --- 613 cc->do_unaligned_access = riscv_cpu_do_unaligned_access; 614 cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; 615 /* For now, mark unmigratable: */ 616 cc->vmsd = &vmstate_riscv_cpu; 617#endif 618 cc->gdb_arch_name = riscv_gdb_arch_name; 619 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 620 cc->tcg_ops.initialize = riscv_translate_init; |
621 cc->tlb_fill = riscv_cpu_tlb_fill; | 621 cc->tcg_ops.tlb_fill = riscv_cpu_tlb_fill; |
622 623 device_class_set_props(dc, riscv_cpu_properties); 624} 625 626char *riscv_isa_string(RISCVCPU *cpu) 627{ 628 int i; 629 const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; --- 73 unchanged lines hidden --- | 622 623 device_class_set_props(dc, riscv_cpu_properties); 624} 625 626char *riscv_isa_string(RISCVCPU *cpu) 627{ 628 int i; 629 const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; --- 73 unchanged lines hidden --- |