fixedpoint-impl.c.inc (f003dd8d81f7d88f4b1f8802309eaa76f6eb223a) fixedpoint-impl.c.inc (4fe0e9db0a834111ae6ddc380986f4f56f28f3b6)
1/*
2 * Power ISA decode for Fixed-Point Facility instructions
3 *
4 * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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479#else
480 qemu_build_not_reached();
481#endif
482 return true;
483}
484
485static bool trans_ADDG6S(DisasContext *ctx, arg_X *a)
486{
1/*
2 * Power ISA decode for Fixed-Point Facility instructions
3 *
4 * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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479#else
480 qemu_build_not_reached();
481#endif
482 return true;
483}
484
485static bool trans_ADDG6S(DisasContext *ctx, arg_X *a)
486{
487 const uint64_t carry_bits = 0x1111111111111111ULL;
488 TCGv t0, t1, carry, zero = tcg_constant_tl(0);
487 const target_ulong carry_bits = (target_ulong)-1 / 0xf;
488 TCGv in1, in2, carryl, carryh, tmp;
489 TCGv zero = tcg_constant_tl(0);
489
490 REQUIRE_INSNS_FLAGS2(ctx, BCDA_ISA206);
491
490
491 REQUIRE_INSNS_FLAGS2(ctx, BCDA_ISA206);
492
492 t0 = tcg_temp_new();
493 t1 = tcg_const_tl(0);
494 carry = tcg_const_tl(0);
493 in1 = cpu_gpr[a->ra];
494 in2 = cpu_gpr[a->rb];
495 tmp = tcg_temp_new();
496 carryl = tcg_temp_new();
497 carryh = tcg_temp_new();
495
498
496 for (int i = 0; i < 16; i++) {
497 tcg_gen_shri_tl(t0, cpu_gpr[a->ra], i * 4);
498 tcg_gen_andi_tl(t0, t0, 0xf);
499 tcg_gen_add_tl(t1, t1, t0);
499 /* Addition with carry. */
500 tcg_gen_add2_tl(carryl, carryh, in1, zero, in2, zero);
501 /* Addition without carry. */
502 tcg_gen_xor_tl(tmp, in1, in2);
503 /* Difference between the two is carry in to each bit. */
504 tcg_gen_xor_tl(carryl, carryl, tmp);
500
505
501 tcg_gen_shri_tl(t0, cpu_gpr[a->rb], i * 4);
502 tcg_gen_andi_tl(t0, t0, 0xf);
503 tcg_gen_add_tl(t1, t1, t0);
506 /*
507 * The carry-out that we're looking for is the carry-in to
508 * the next nibble. Shift the double-word down one nibble,
509 * which puts all of the bits back into one word.
510 */
511 tcg_gen_extract2_tl(carryl, carryl, carryh, 4);
504
512
505 tcg_gen_andi_tl(t1, t1, 0x10);
506 tcg_gen_setcond_tl(TCG_COND_NE, t1, t1, zero);
507
508 tcg_gen_shli_tl(t0, t1, i * 4);
509 tcg_gen_or_tl(carry, carry, t0);
510 }
511
512 tcg_gen_xori_tl(carry, carry, (target_long)carry_bits);
513 tcg_gen_muli_tl(cpu_gpr[a->rt], carry, 6);
513 /* Invert, isolate the carry bits, and produce 6's. */
514 tcg_gen_andc_tl(carryl, tcg_constant_tl(carry_bits), carryl);
515 tcg_gen_muli_tl(cpu_gpr[a->rt], carryl, 6);
514 return true;
515}
516
517static bool trans_CDTBCD(DisasContext *ctx, arg_X_sa *a)
518{
519 REQUIRE_INSNS_FLAGS2(ctx, BCDA_ISA206);
520 gen_helper_CDTBCD(cpu_gpr[a->ra], cpu_gpr[a->rs]);
521 return true;

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517}
518
519static bool trans_CDTBCD(DisasContext *ctx, arg_X_sa *a)
520{
521 REQUIRE_INSNS_FLAGS2(ctx, BCDA_ISA206);
522 gen_helper_CDTBCD(cpu_gpr[a->ra], cpu_gpr[a->rs]);
523 return true;

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