translate.c (e65472c7bc413d79faa61eb1d05c540b03945894) translate.c (14776ab5a12972ea439c7fb2203a4c15a09094b4)
1/*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public

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158 uint32_t exception;
159 /* Routine used to access memory */
160 bool pr, hv, dr, le_mode;
161 bool lazy_tlb_flush;
162 bool need_access_type;
163 int mem_idx;
164 int access_type;
165 /* Translation flags */
1/*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public

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158 uint32_t exception;
159 /* Routine used to access memory */
160 bool pr, hv, dr, le_mode;
161 bool lazy_tlb_flush;
162 bool need_access_type;
163 int mem_idx;
164 int access_type;
165 /* Translation flags */
166 TCGMemOp default_tcg_memop_mask;
166 MemOp default_tcg_memop_mask;
167#if defined(TARGET_PPC64)
168 bool sf_mode;
169 bool has_cfar;
170#endif
171 bool fpu_enabled;
172 bool altivec_enabled;
173 bool vsx_enabled;
174 bool spe_enabled;

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3137 gen_check_tlb_flush(ctx, false);
3138 }
3139 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3140 gen_stop_exception(ctx);
3141}
3142
3143#define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3144
167#if defined(TARGET_PPC64)
168 bool sf_mode;
169 bool has_cfar;
170#endif
171 bool fpu_enabled;
172 bool altivec_enabled;
173 bool vsx_enabled;
174 bool spe_enabled;

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3137 gen_check_tlb_flush(ctx, false);
3138 }
3139 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3140 gen_stop_exception(ctx);
3141}
3142
3143#define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3144
3145static void gen_load_locked(DisasContext *ctx, TCGMemOp memop)
3145static void gen_load_locked(DisasContext *ctx, MemOp memop)
3146{
3147 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3148 TCGv t0 = tcg_temp_new();
3149
3150 gen_set_access_type(ctx, ACCESS_RES);
3151 gen_addr_reg_index(ctx, t0);
3152 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN);
3153 tcg_gen_mov_tl(cpu_reserve, t0);

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3162 gen_load_locked(ctx, memop); \
3163}
3164
3165/* lwarx */
3166LARX(lbarx, DEF_MEMOP(MO_UB))
3167LARX(lharx, DEF_MEMOP(MO_UW))
3168LARX(lwarx, DEF_MEMOP(MO_UL))
3169
3146{
3147 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3148 TCGv t0 = tcg_temp_new();
3149
3150 gen_set_access_type(ctx, ACCESS_RES);
3151 gen_addr_reg_index(ctx, t0);
3152 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN);
3153 tcg_gen_mov_tl(cpu_reserve, t0);

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3162 gen_load_locked(ctx, memop); \
3163}
3164
3165/* lwarx */
3166LARX(lbarx, DEF_MEMOP(MO_UB))
3167LARX(lharx, DEF_MEMOP(MO_UW))
3168LARX(lwarx, DEF_MEMOP(MO_UL))
3169
3170static void gen_fetch_inc_conditional(DisasContext *ctx, TCGMemOp memop,
3170static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop,
3171 TCGv EA, TCGCond cond, int addend)
3172{
3173 TCGv t = tcg_temp_new();
3174 TCGv t2 = tcg_temp_new();
3175 TCGv u = tcg_temp_new();
3176
3177 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
3178 tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop));

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3188 tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1));
3189 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u);
3190
3191 tcg_temp_free(t);
3192 tcg_temp_free(t2);
3193 tcg_temp_free(u);
3194}
3195
3171 TCGv EA, TCGCond cond, int addend)
3172{
3173 TCGv t = tcg_temp_new();
3174 TCGv t2 = tcg_temp_new();
3175 TCGv u = tcg_temp_new();
3176
3177 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
3178 tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop));

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3188 tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1));
3189 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u);
3190
3191 tcg_temp_free(t);
3192 tcg_temp_free(t2);
3193 tcg_temp_free(u);
3194}
3195
3196static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop)
3196static void gen_ld_atomic(DisasContext *ctx, MemOp memop)
3197{
3198 uint32_t gpr_FC = FC(ctx->opcode);
3199 TCGv EA = tcg_temp_new();
3200 int rt = rD(ctx->opcode);
3201 bool need_serial;
3202 TCGv src, dst;
3203
3204 gen_addr_register(ctx, EA);

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3301
3302#ifdef TARGET_PPC64
3303static void gen_ldat(DisasContext *ctx)
3304{
3305 gen_ld_atomic(ctx, DEF_MEMOP(MO_Q));
3306}
3307#endif
3308
3197{
3198 uint32_t gpr_FC = FC(ctx->opcode);
3199 TCGv EA = tcg_temp_new();
3200 int rt = rD(ctx->opcode);
3201 bool need_serial;
3202 TCGv src, dst;
3203
3204 gen_addr_register(ctx, EA);

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3301
3302#ifdef TARGET_PPC64
3303static void gen_ldat(DisasContext *ctx)
3304{
3305 gen_ld_atomic(ctx, DEF_MEMOP(MO_Q));
3306}
3307#endif
3308
3309static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop)
3309static void gen_st_atomic(DisasContext *ctx, MemOp memop)
3310{
3311 uint32_t gpr_FC = FC(ctx->opcode);
3312 TCGv EA = tcg_temp_new();
3313 TCGv src, discard;
3314
3315 gen_addr_register(ctx, EA);
3316 src = cpu_gpr[rD(ctx->opcode)];
3317 discard = tcg_temp_new();

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3384
3385#ifdef TARGET_PPC64
3386static void gen_stdat(DisasContext *ctx)
3387{
3388 gen_st_atomic(ctx, DEF_MEMOP(MO_Q));
3389}
3390#endif
3391
3310{
3311 uint32_t gpr_FC = FC(ctx->opcode);
3312 TCGv EA = tcg_temp_new();
3313 TCGv src, discard;
3314
3315 gen_addr_register(ctx, EA);
3316 src = cpu_gpr[rD(ctx->opcode)];
3317 discard = tcg_temp_new();

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3384
3385#ifdef TARGET_PPC64
3386static void gen_stdat(DisasContext *ctx)
3387{
3388 gen_st_atomic(ctx, DEF_MEMOP(MO_Q));
3389}
3390#endif
3391
3392static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop)
3392static void gen_conditional_store(DisasContext *ctx, MemOp memop)
3393{
3394 TCGLabel *l1 = gen_new_label();
3395 TCGLabel *l2 = gen_new_label();
3396 TCGv t0 = tcg_temp_new();
3397 int reg = rS(ctx->opcode);
3398
3399 gen_set_access_type(ctx, ACCESS_RES);
3400 gen_addr_reg_index(ctx, t0);

--- 4576 unchanged lines hidden --- 		3393{
3394 TCGLabel *l1 = gen_new_label();
3395 TCGLabel *l2 = gen_new_label();
3396 TCGv t0 = tcg_temp_new();
3397 int reg = rS(ctx->opcode);
3398
3399 gen_set_access_type(ctx, ACCESS_RES);
3400 gen_addr_reg_index(ctx, t0);

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