mmu-radix64.c (077a370499bb100237e291da9a06e6adbcd89335) mmu-radix64.c (51806b545834e0902dd2d17d1f66c7a2d83422f3)
1/*
2 * PowerPC Radix MMU mulation helpers for QEMU.
3 *
4 * Copyright (c) 2016 Suraj Jitindar Singh, IBM Corporation
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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458 * +-------------+----------------+---------------+
459 * | Relocation | Partition | No |
460 * | = Off | Scoped | Translation |
461 * Relocation +-------------+----------------+---------------+
462 * | Relocation | Partition & | Process |
463 * | = On | Process Scoped | Scoped |
464 * +-------------+----------------+---------------+
465 */
1/*
2 * PowerPC Radix MMU mulation helpers for QEMU.
3 *
4 * Copyright (c) 2016 Suraj Jitindar Singh, IBM Corporation
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

--- 449 unchanged lines hidden (view full) ---

458 * +-------------+----------------+---------------+
459 * | Relocation | Partition | No |
460 * | = Off | Scoped | Translation |
461 * Relocation +-------------+----------------+---------------+
462 * | Relocation | Partition & | Process |
463 * | = On | Process Scoped | Scoped |
464 * +-------------+----------------+---------------+
465 */
466static bool ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr,
467 MMUAccessType access_type,
468 hwaddr *raddr, int *psizep, int *protp,
469 bool guest_visible)
466bool ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
467 hwaddr *raddr, int *psizep, int *protp,
468 bool guest_visible)
470{
471 CPUPPCState *env = &cpu->env;
472 uint64_t lpid, pid;
473 ppc_v3_pate_t pate;
474 int psize, prot;
475 hwaddr g_raddr;
476 bool relocation;
477

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579 *protp &= prot;
580 } else {
581 *raddr = g_raddr;
582 }
583 }
584
585 return true;
586}
469{
470 CPUPPCState *env = &cpu->env;
471 uint64_t lpid, pid;
472 ppc_v3_pate_t pate;
473 int psize, prot;
474 hwaddr g_raddr;
475 bool relocation;
476

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578 *protp &= prot;
579 } else {
580 *raddr = g_raddr;
581 }
582 }
583
584 return true;
585}
587
588int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
589 MMUAccessType access_type, int mmu_idx)
590{
591 CPUState *cs = CPU(cpu);
592 int page_size, prot;
593 hwaddr raddr;
594
595 /* Translate eaddr to raddr (where raddr is addr qemu needs for access) */
596 if (!ppc_radix64_xlate(cpu, eaddr, access_type, &raddr,
597 &page_size, &prot, true)) {
598 return 1;
599 }
600
601 tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
602 prot, mmu_idx, 1UL << page_size);
603 return 0;
604}
605
606hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr)
607{
608 int psize, prot;
609 hwaddr raddr;
610
611 if (!ppc_radix64_xlate(cpu, eaddr, MMU_DATA_LOAD, &raddr,
612 &psize, &prot, false)) {
613 return -1;
614 }
615
616 return raddr & TARGET_PAGE_MASK;
617}