mmu-hash64.c (1a8c647bbd72f70c2cd8d369b3aa3e71a57ac3d8) mmu-hash64.c (51806b545834e0902dd2d17d1f66c7a2d83422f3)
1/*
2 * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (c) 2013 David Gibson, IBM Corporation
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public

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868 }
869
870 error_report("Bad page size encoding in LPCR[VRMASD]; LPCR=0x"
871 TARGET_FMT_lx, lpcr);
872
873 return -1;
874}
875
1/*
2 * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (c) 2013 David Gibson, IBM Corporation
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public

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868 }
869
870 error_report("Bad page size encoding in LPCR[VRMASD]; LPCR=0x"
871 TARGET_FMT_lx, lpcr);
872
873 return -1;
874}
875
876static bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr,
877 MMUAccessType access_type,
878 hwaddr *raddrp, int *psizep, int *protp,
879 bool guest_visible)
876bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
877 hwaddr *raddrp, int *psizep, int *protp,
878 bool guest_visible)
880{
881 CPUState *cs = CPU(cpu);
882 CPUPPCState *env = &cpu->env;
883 ppc_slb_t vrma_slbe;
884 ppc_slb_t *slb;
885 unsigned apshift;
886 hwaddr ptex;
887 ppc_hash_pte64_t pte;

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1089 /* 7. Determine the real address from the PTE */
1090
1091 *raddrp = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr);
1092 *protp = prot;
1093 *psizep = apshift;
1094 return true;
1095}
1096
879{
880 CPUState *cs = CPU(cpu);
881 CPUPPCState *env = &cpu->env;
882 ppc_slb_t vrma_slbe;
883 ppc_slb_t *slb;
884 unsigned apshift;
885 hwaddr ptex;
886 ppc_hash_pte64_t pte;

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1088 /* 7. Determine the real address from the PTE */
1089
1090 *raddrp = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr);
1091 *protp = prot;
1092 *psizep = apshift;
1093 return true;
1094}
1095
1097int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
1098 MMUAccessType access_type, int mmu_idx)
1099{
1100 CPUState *cs = CPU(cpu);
1101 int page_size, prot;
1102 hwaddr raddr;
1103
1104 if (!ppc_hash64_xlate(cpu, eaddr, access_type, &raddr,
1105 &page_size, &prot, true)) {
1106 return 1;
1107 }
1108
1109 tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
1110 prot, mmu_idx, 1UL << page_size);
1111 return 0;
1112}
1113
1114hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr)
1115{
1116 int psize, prot;
1117 hwaddr raddr;
1118
1119 if (!ppc_hash64_xlate(cpu, eaddr, MMU_DATA_LOAD, &raddr,
1120 &psize, &prot, false)) {
1121 return -1;
1122 }
1123
1124 return raddr & TARGET_PAGE_MASK;
1125}
1126
1127void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex,
1128 target_ulong pte0, target_ulong pte1)
1129{
1130 /*
1131 * XXX: given the fact that there are too many segments to
1132 * invalidate, and we still don't have a tlb_flush_mask(env, n,
1133 * mask) in QEMU, we just invalidate all TLBs
1134 */

--- 76 unchanged lines hidden --- 		1096void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex,
1097 target_ulong pte0, target_ulong pte1)
1098{
1099 /*
1100 * XXX: given the fact that there are too many segments to
1101 * invalidate, and we still don't have a tlb_flush_mask(env, n,
1102 * mask) in QEMU, we just invalidate all TLBs
1103 */

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