cpu.h (c9d5aedf40cfa0d68a6a4c020d14f8e6116a369e) cpu.h (2736432ffc30b74fc72858854e62b62253b685ff)
1/*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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1259 int access_type;
1260
1261#if !defined(CONFIG_USER_ONLY)
1262 /* MMU context, only relevant for full system emulation */
1263#if defined(TARGET_PPC64)
1264 ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */
1265 struct CPUBreakpoint *ciabr_breakpoint;
1266 struct CPUWatchpoint *dawr0_watchpoint;
1/*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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1259 int access_type;
1260
1261#if !defined(CONFIG_USER_ONLY)
1262 /* MMU context, only relevant for full system emulation */
1263#if defined(TARGET_PPC64)
1264 ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */
1265 struct CPUBreakpoint *ciabr_breakpoint;
1266 struct CPUWatchpoint *dawr0_watchpoint;
1267
1268 /* POWER CPU regs/state */
1269 target_ulong scratch[8]; /* SCRATCH registers (shared across core) */
1267#endif
1268 target_ulong sr[32]; /* segment registers */
1269 uint32_t nb_BATs; /* number of BATs */
1270 target_ulong DBAT[2][8];
1271 target_ulong IBAT[2][8];
1272 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1273 int32_t nb_tlb; /* Total number of TLB */
1274 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */

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1801#define SPR_USPRG7 (0x107)
1802#define SPR_TBL (0x10C)
1803#define SPR_TBU (0x10D)
1804#define SPR_SPRG0 (0x110)
1805#define SPR_SPRG1 (0x111)
1806#define SPR_SPRG2 (0x112)
1807#define SPR_SPRG3 (0x113)
1808#define SPR_SPRG4 (0x114)
1270#endif
1271 target_ulong sr[32]; /* segment registers */
1272 uint32_t nb_BATs; /* number of BATs */
1273 target_ulong DBAT[2][8];
1274 target_ulong IBAT[2][8];
1275 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1276 int32_t nb_tlb; /* Total number of TLB */
1277 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */

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1804#define SPR_USPRG7 (0x107)
1805#define SPR_TBL (0x10C)
1806#define SPR_TBU (0x10D)
1807#define SPR_SPRG0 (0x110)
1808#define SPR_SPRG1 (0x111)
1809#define SPR_SPRG2 (0x112)
1810#define SPR_SPRG3 (0x113)
1811#define SPR_SPRG4 (0x114)
1809#define SPR_SCOMC (0x114)
1812#define SPR_POWER_SPRC (0x114)
1810#define SPR_SPRG5 (0x115)
1813#define SPR_SPRG5 (0x115)
1811#define SPR_SCOMD (0x115)
1814#define SPR_POWER_SPRD (0x115)
1812#define SPR_SPRG6 (0x116)
1813#define SPR_SPRG7 (0x117)
1814#define SPR_ASR (0x118)
1815#define SPR_EAR (0x11A)
1816#define SPR_WR_TBL (0x11C)
1817#define SPR_WR_TBU (0x11D)
1818#define SPR_TBU40 (0x11E)
1819#define SPR_SVR (0x11E)

--- 1250 unchanged lines hidden --- 		1815#define SPR_SPRG6 (0x116)
1816#define SPR_SPRG7 (0x117)
1817#define SPR_ASR (0x118)
1818#define SPR_EAR (0x11A)
1819#define SPR_WR_TBL (0x11C)
1820#define SPR_WR_TBU (0x11D)
1821#define SPR_TBU40 (0x11E)
1822#define SPR_SVR (0x11E)

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