cpu.h (56ced49760df758650e852361b1b1a359ca6c904) cpu.h (2df4fe7abeed5be7c4350c12cfe33242261b28ef)
1/*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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580 /* Has Transaction Memory (ISA 2.07) */
581 POWERPC_FLAG_TM = 0x00100000,
582 /* Has SCV (ISA 3.00) */
583 POWERPC_FLAG_SCV = 0x00200000,
584 /* Has HID0 for LE bit (601) */
585 POWERPC_FLAG_HID0_LE = 0x00400000,
586};
587
1/*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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580 /* Has Transaction Memory (ISA 2.07) */
581 POWERPC_FLAG_TM = 0x00100000,
582 /* Has SCV (ISA 3.00) */
583 POWERPC_FLAG_SCV = 0x00200000,
584 /* Has HID0 for LE bit (601) */
585 POWERPC_FLAG_HID0_LE = 0x00400000,
586};
587
588/*
589 * Bits for env->hflags.
590 *
591 * Most of these bits overlap with corresponding bits in MSR,
592 * but some come from other sources. Those that do come from
593 * the MSR are validated in hreg_compute_hflags.
594 */
595enum {
596 HFLAGS_LE = 0, /* MSR_LE -- comes from elsewhere on 601 */
597 HFLAGS_HV = 1, /* computed from MSR_HV and other state */
598 HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */
599 HFLAGS_DR = 4, /* MSR_DR */
600 HFLAGS_IR = 5, /* MSR_IR */
601 HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */
602 HFLAGS_VSX = 7, /* from MSR_VSX if cpu has VSX; avoid overlap w/ MSR_AP */
603 HFLAGS_TM = 8, /* computed from MSR_TM */
604 HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */
605 HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */
606 HFLAGS_FP = 13, /* MSR_FP */
607 HFLAGS_PR = 14, /* MSR_PR */
608 HFLAGS_SA = 22, /* MSR_SA */
609 HFLAGS_AP = 23, /* MSR_AP */
610 HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */
611};
612
588/*****************************************************************************/
589/* Floating point status and control register */
590#define FPSCR_DRN2 34 /* Decimal Floating-Point rounding control */
591#define FPSCR_DRN1 33 /* Decimal Floating-Point rounding control */
592#define FPSCR_DRN0 32 /* Decimal Floating-Point rounding control */
593#define FPSCR_FX 31 /* Floating-point exception summary */
594#define FPSCR_FEX 30 /* Floating-point enabled exception summary */
595#define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */

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613/*****************************************************************************/
614/* Floating point status and control register */
615#define FPSCR_DRN2 34 /* Decimal Floating-Point rounding control */
616#define FPSCR_DRN1 33 /* Decimal Floating-Point rounding control */
617#define FPSCR_DRN0 32 /* Decimal Floating-Point rounding control */
618#define FPSCR_FX 31 /* Floating-point exception summary */
619#define FPSCR_FEX 30 /* Floating-point enabled exception summary */
620#define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */

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