cpu.h (d8276573da58e8ce78dab8c46dd660efd664bcb7) cpu.h (74433bf083b0766aba81534f92de13194f23ff3e)
1/*
2 * OpenRISC virtual CPU header.
3 *
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef OPENRISC_CPU_H
21#define OPENRISC_CPU_H
22
1/*
2 * OpenRISC virtual CPU header.
3 *
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef OPENRISC_CPU_H
21#define OPENRISC_CPU_H
22
23#define TARGET_LONG_BITS 32
23#include "qemu-common.h"
24#include "exec/cpu-defs.h"
25#include "qom/cpu.h"
24
25#define CPUArchState struct CPUOpenRISCState
26
27/* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
28struct OpenRISCCPU;
29
26
27#define CPUArchState struct CPUOpenRISCState
28
29/* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
30struct OpenRISCCPU;
31
30#include "qemu-common.h"
31#include "exec/cpu-defs.h"
32#include "qom/cpu.h"
33
34#define TYPE_OPENRISC_CPU "or1k-cpu"
35
36#define OPENRISC_CPU_CLASS(klass) \
37 OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
38#define OPENRISC_CPU(obj) \
39 OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU)
40#define OPENRISC_CPU_GET_CLASS(obj) \
41 OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU)

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51 /*< private >*/
52 CPUClass parent_class;
53 /*< public >*/
54
55 DeviceRealize parent_realize;
56 void (*parent_reset)(CPUState *cpu);
57} OpenRISCCPUClass;
58
32#define TYPE_OPENRISC_CPU "or1k-cpu"
33
34#define OPENRISC_CPU_CLASS(klass) \
35 OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
36#define OPENRISC_CPU(obj) \
37 OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU)
38#define OPENRISC_CPU_GET_CLASS(obj) \
39 OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU)

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49 /*< private >*/
50 CPUClass parent_class;
51 /*< public >*/
52
53 DeviceRealize parent_realize;
54 void (*parent_reset)(CPUState *cpu);
55} OpenRISCCPUClass;
56
59#define NB_MMU_MODES 3
60#define TARGET_INSN_START_EXTRA_WORDS 1
61
62enum {
63 MMU_NOMMU_IDX = 0,
64 MMU_SUPERVISOR_IDX = 1,
65 MMU_USER_IDX = 2,
66};
67
57#define TARGET_INSN_START_EXTRA_WORDS 1
58
59enum {
60 MMU_NOMMU_IDX = 0,
61 MMU_SUPERVISOR_IDX = 1,
62 MMU_USER_IDX = 2,
63};
64
68#define TARGET_PAGE_BITS 13
69
70#define TARGET_PHYS_ADDR_SPACE_BITS 32
71#define TARGET_VIRT_ADDR_SPACE_BITS 32
72
73#define SET_FP_CAUSE(reg, v) do {\
74 (reg) = ((reg) & ~(0x3f << 12)) | \
75 ((v & 0x3f) << 12);\
76 } while (0)
77#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
78#define UPDATE_FP_FLAGS(reg, v) do {\
79 (reg) |= ((v & 0x1f) << 2);\
80 } while (0)

--- 356 unchanged lines hidden --- 		65#define SET_FP_CAUSE(reg, v) do {\
66 (reg) = ((reg) & ~(0x3f << 12)) | \
67 ((v & 0x3f) << 12);\
68 } while (0)
69#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
70#define UPDATE_FP_FLAGS(reg, v) do {\
71 (reg) |= ((v & 0x1f) << 2);\
72 } while (0)

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