| cpu.c (48c1a3e303b5a2cca48679645ad3fbb914db741a) | cpu.c (e124536f37377cff5d68925d4976ad604d0ebf3a) |
|---|---|
| 1/* 2 * QEMU OpenRISC CPU 3 * 4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either --- 178 unchanged lines hidden (view full) --- 187 cc->class_by_name = openrisc_cpu_class_by_name; 188 cc->has_work = openrisc_cpu_has_work; 189 cc->do_interrupt = openrisc_cpu_do_interrupt; 190 cc->tcg_ops.cpu_exec_interrupt = openrisc_cpu_exec_interrupt; 191 cc->dump_state = openrisc_cpu_dump_state; 192 cc->set_pc = openrisc_cpu_set_pc; 193 cc->gdb_read_register = openrisc_cpu_gdb_read_register; 194 cc->gdb_write_register = openrisc_cpu_gdb_write_register; | 1/* 2 * QEMU OpenRISC CPU 3 * 4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either --- 178 unchanged lines hidden (view full) --- 187 cc->class_by_name = openrisc_cpu_class_by_name; 188 cc->has_work = openrisc_cpu_has_work; 189 cc->do_interrupt = openrisc_cpu_do_interrupt; 190 cc->tcg_ops.cpu_exec_interrupt = openrisc_cpu_exec_interrupt; 191 cc->dump_state = openrisc_cpu_dump_state; 192 cc->set_pc = openrisc_cpu_set_pc; 193 cc->gdb_read_register = openrisc_cpu_gdb_read_register; 194 cc->gdb_write_register = openrisc_cpu_gdb_write_register; |
| 195 cc->tlb_fill = openrisc_cpu_tlb_fill; | 195 cc->tcg_ops.tlb_fill = openrisc_cpu_tlb_fill; |
| 196#ifndef CONFIG_USER_ONLY 197 cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug; 198 dc->vmsd = &vmstate_openrisc_cpu; 199#endif 200 cc->gdb_num_core_regs = 32 + 3; 201 cc->tcg_ops.initialize = openrisc_translate_init; 202 cc->disas_set_info = openrisc_disas_set_info; 203} --- 65 unchanged lines hidden --- | 196#ifndef CONFIG_USER_ONLY 197 cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug; 198 dc->vmsd = &vmstate_openrisc_cpu; 199#endif 200 cc->gdb_num_core_regs = 32 + 3; 201 cc->tcg_ops.initialize = openrisc_translate_init; 202 cc->disas_set_info = openrisc_disas_set_info; 203} --- 65 unchanged lines hidden --- |