cpu.h (d1e8e8ecc3d2a1a72504912d671f1cbbac1b06e5) cpu.h (1f5c00cfdb8114c1e3a13426588ceb64f82c9ddb)
1#ifndef MIPS_CPU_H
2#define MIPS_CPU_H
3
4//#define DEBUG_OP
5
6#define ALIGNED_ONLY
7
8#define CPUArchState struct CPUMIPSState

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602 target_ulong bcond; /* Branch condition (if needed) */
603
604 int SYNCI_Step; /* Address step size for SYNCI */
605 int CCRes; /* Cycle count resolution/divisor */
606 uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
607 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
608 int insn_flags; /* Supported instruction set */
609
1#ifndef MIPS_CPU_H
2#define MIPS_CPU_H
3
4//#define DEBUG_OP
5
6#define ALIGNED_ONLY
7
8#define CPUArchState struct CPUMIPSState

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602 target_ulong bcond; /* Branch condition (if needed) */
603
604 int SYNCI_Step; /* Address step size for SYNCI */
605 int CCRes; /* Cycle count resolution/divisor */
606 uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
607 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
608 int insn_flags; /* Supported instruction set */
609
610 /* Fields up to this point are cleared by a CPU reset */
611 struct {} end_reset_fields;
612
610 CPU_COMMON
611
612 /* Fields from here on are preserved across CPU reset. */
613 CPUMIPSMVPContext *mvp;
614#if !defined(CONFIG_USER_ONLY)
615 CPUMIPSTLBContext *tlb;
616#endif
617

--- 452 unchanged lines hidden --- 		613 CPU_COMMON
614
615 /* Fields from here on are preserved across CPU reset. */
616 CPUMIPSMVPContext *mvp;
617#if !defined(CONFIG_USER_ONLY)
618 CPUMIPSTLBContext *tlb;
619#endif
620

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