translate.c (ccf628b7939c542cf9e46e9aaa2b0acf0888ec52) translate.c (39db007eda4310f305fdbc712d59d99284bf11d4)
1/*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public

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54#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */
55
56static TCGv_i32 env_debug;
57static TCGv_i32 cpu_R[32];
58static TCGv_i32 cpu_pc;
59static TCGv_i32 cpu_msr;
60static TCGv_i64 cpu_ear;
61static TCGv_i32 cpu_esr;
1/*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public

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54#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */
55
56static TCGv_i32 env_debug;
57static TCGv_i32 cpu_R[32];
58static TCGv_i32 cpu_pc;
59static TCGv_i32 cpu_msr;
60static TCGv_i64 cpu_ear;
61static TCGv_i32 cpu_esr;
62static TCGv_i64 cpu_edr;
63static TCGv_i32 env_imm;
64static TCGv_i32 env_btaken;
65static TCGv_i32 cpu_btarget;
66static TCGv_i32 env_iflags;
67static TCGv env_res_addr;
68static TCGv_i32 env_res_val;
69
70#include "exec/gen-icount.h"

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543 tcg_gen_st_i32(cpu_R[dc->ra],
544 cpu_env, offsetof(CPUMBState, fsr));
545 break;
546 case SR_BTR:
547 tcg_gen_st_i32(cpu_R[dc->ra],
548 cpu_env, offsetof(CPUMBState, btr));
549 break;
550 case SR_EDR:
62static TCGv_i32 env_imm;
63static TCGv_i32 env_btaken;
64static TCGv_i32 cpu_btarget;
65static TCGv_i32 env_iflags;
66static TCGv env_res_addr;
67static TCGv_i32 env_res_val;
68
69#include "exec/gen-icount.h"

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542 tcg_gen_st_i32(cpu_R[dc->ra],
543 cpu_env, offsetof(CPUMBState, fsr));
544 break;
545 case SR_BTR:
546 tcg_gen_st_i32(cpu_R[dc->ra],
547 cpu_env, offsetof(CPUMBState, btr));
548 break;
549 case SR_EDR:
551 tcg_gen_extu_i32_i64(cpu_edr, cpu_R[dc->ra]);
550 tcg_gen_st_i32(cpu_R[dc->ra],
551 cpu_env, offsetof(CPUMBState, edr));
552 break;
553 case 0x800:
554 tcg_gen_st_i32(cpu_R[dc->ra],
555 cpu_env, offsetof(CPUMBState, slr));
556 break;
557 case 0x802:
558 tcg_gen_st_i32(cpu_R[dc->ra],
559 cpu_env, offsetof(CPUMBState, shr));

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586 tcg_gen_ld_i32(cpu_R[dc->rd],
587 cpu_env, offsetof(CPUMBState, fsr));
588 break;
589 case SR_BTR:
590 tcg_gen_ld_i32(cpu_R[dc->rd],
591 cpu_env, offsetof(CPUMBState, btr));
592 break;
593 case SR_EDR:
552 break;
553 case 0x800:
554 tcg_gen_st_i32(cpu_R[dc->ra],
555 cpu_env, offsetof(CPUMBState, slr));
556 break;
557 case 0x802:
558 tcg_gen_st_i32(cpu_R[dc->ra],
559 cpu_env, offsetof(CPUMBState, shr));

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586 tcg_gen_ld_i32(cpu_R[dc->rd],
587 cpu_env, offsetof(CPUMBState, fsr));
588 break;
589 case SR_BTR:
590 tcg_gen_ld_i32(cpu_R[dc->rd],
591 cpu_env, offsetof(CPUMBState, btr));
592 break;
593 case SR_EDR:
594 tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_edr);
594 tcg_gen_ld_i32(cpu_R[dc->rd],
595 cpu_env, offsetof(CPUMBState, edr));
595 break;
596 case 0x800:
597 tcg_gen_ld_i32(cpu_R[dc->rd],
598 cpu_env, offsetof(CPUMBState, slr));
599 break;
600 case 0x802:
601 tcg_gen_ld_i32(cpu_R[dc->rd],
602 cpu_env, offsetof(CPUMBState, shr));

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1813 for (i = 0; i < 12; i++) {
1814 qemu_fprintf(f, "rpvr%2.2d=%8.8x ", i, env->pvr.regs[i]);
1815 if ((i + 1) % 4 == 0) {
1816 qemu_fprintf(f, "\n");
1817 }
1818 }
1819
1820 /* Registers that aren't modeled are reported as 0 */
596 break;
597 case 0x800:
598 tcg_gen_ld_i32(cpu_R[dc->rd],
599 cpu_env, offsetof(CPUMBState, slr));
600 break;
601 case 0x802:
602 tcg_gen_ld_i32(cpu_R[dc->rd],
603 cpu_env, offsetof(CPUMBState, shr));

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1814 for (i = 0; i < 12; i++) {
1815 qemu_fprintf(f, "rpvr%2.2d=%8.8x ", i, env->pvr.regs[i]);
1816 if ((i + 1) % 4 == 0) {
1817 qemu_fprintf(f, "\n");
1818 }
1819 }
1820
1821 /* Registers that aren't modeled are reported as 0 */
1821 qemu_fprintf(f, "redr=%" PRIx64 " rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 "
1822 qemu_fprintf(f, "redr=%x rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 "
1822 "rtlblo=0 rtlbhi=0\n", env->edr);
1823 qemu_fprintf(f, "slr=%x shr=%x\n", env->slr, env->shr);
1824 for (i = 0; i < 32; i++) {
1825 qemu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1826 if ((i + 1) % 4 == 0)
1827 qemu_fprintf(f, "\n");
1828 }
1829 qemu_fprintf(f, "\n\n");

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1863 cpu_pc =
1864 tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc");
1865 cpu_msr =
1866 tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, msr), "rmsr");
1867 cpu_ear =
1868 tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear");
1869 cpu_esr =
1870 tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr");
1823 "rtlblo=0 rtlbhi=0\n", env->edr);
1824 qemu_fprintf(f, "slr=%x shr=%x\n", env->slr, env->shr);
1825 for (i = 0; i < 32; i++) {
1826 qemu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1827 if ((i + 1) % 4 == 0)
1828 qemu_fprintf(f, "\n");
1829 }
1830 qemu_fprintf(f, "\n\n");

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1864 cpu_pc =
1865 tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc");
1866 cpu_msr =
1867 tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, msr), "rmsr");
1868 cpu_ear =
1869 tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear");
1870 cpu_esr =
1871 tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr");
1871 cpu_edr =
1872 tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr");
1873}
1874
1875void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb,
1876 target_ulong *data)
1877{
1878 env->pc = data[0];
1879}
1872}
1873
1874void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb,
1875 target_ulong *data)
1876{
1877 env->pc = data[0];
1878}