translate.c (6fbf78f24a43c57925dc4e789dc236cdec443987) translate.c (af20a93acb5e9da63976e113656d09e4bcbdddac)
1/*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public

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98static const char *regnames[] =
99{
100 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
101 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
102 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
103 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
104};
105
1/*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public

--- 89 unchanged lines hidden (view full) ---

98static const char *regnames[] =
99{
100 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
101 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
102 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
103 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
104};
105
106static const char *special_regnames[] =
107{
108 "rpc", "rmsr", "sr2", "rear", "sr4", "resr", "sr6", "rfsr",
109 "sr8", "sr9", "sr10", "rbtr", "sr12", "redr"
110};
111
112static inline void t_sync_flags(DisasContext *dc)
113{
114 /* Synch the tb dependent flags between translator and runtime. */
115 if (dc->tb_flags != dc->synced_flags) {
116 tcg_gen_movi_i32(env_iflags, dc->tb_flags);
117 dc->synced_flags = dc->tb_flags;
118 }
119}

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1823 qemu_fprintf(f, "rpvr%2.2d=%8.8x ", i, env->pvr.regs[i]);
1824 if ((i + 1) % 4 == 0) {
1825 qemu_fprintf(f, "\n");
1826 }
1827 }
1828
1829 /* Registers that aren't modeled are reported as 0 */
1830 qemu_fprintf(f, "redr=%" PRIx64 " rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 "
106static inline void t_sync_flags(DisasContext *dc)
107{
108 /* Synch the tb dependent flags between translator and runtime. */
109 if (dc->tb_flags != dc->synced_flags) {
110 tcg_gen_movi_i32(env_iflags, dc->tb_flags);
111 dc->synced_flags = dc->tb_flags;
112 }
113}

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1817 qemu_fprintf(f, "rpvr%2.2d=%8.8x ", i, env->pvr.regs[i]);
1818 if ((i + 1) % 4 == 0) {
1819 qemu_fprintf(f, "\n");
1820 }
1821 }
1822
1823 /* Registers that aren't modeled are reported as 0 */
1824 qemu_fprintf(f, "redr=%" PRIx64 " rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 "
1831 "rtlblo=0 rtlbhi=0\n", env->sregs[SR_EDR]);
1825 "rtlblo=0 rtlbhi=0\n", env->edr);
1832 qemu_fprintf(f, "slr=%x shr=%x\n", env->slr, env->shr);
1833 for (i = 0; i < 32; i++) {
1834 qemu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1835 if ((i + 1) % 4 == 0)
1836 qemu_fprintf(f, "\n");
1837 }
1838 qemu_fprintf(f, "\n\n");
1839}

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1876 cpu_SR[SR_EAR] =
1877 tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear");
1878 cpu_SR[SR_ESR] =
1879 tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr");
1880 cpu_SR[SR_FSR] =
1881 tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr");
1882 cpu_SR[SR_BTR] =
1883 tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr");
1826 qemu_fprintf(f, "slr=%x shr=%x\n", env->slr, env->shr);
1827 for (i = 0; i < 32; i++) {
1828 qemu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1829 if ((i + 1) % 4 == 0)
1830 qemu_fprintf(f, "\n");
1831 }
1832 qemu_fprintf(f, "\n\n");
1833}

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1870 cpu_SR[SR_EAR] =
1871 tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear");
1872 cpu_SR[SR_ESR] =
1873 tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr");
1874 cpu_SR[SR_FSR] =
1875 tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr");
1876 cpu_SR[SR_BTR] =
1877 tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr");
1884
1885 for (i = SR_BTR + 1; i < ARRAY_SIZE(cpu_SR); i++) {
1886 cpu_SR[i] = tcg_global_mem_new_i64(cpu_env,
1887 offsetof(CPUMBState, sregs[i]),
1888 special_regnames[i]);
1889 }
1878 cpu_SR[SR_EDR] =
1879 tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr");
1890}
1891
1892void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb,
1893 target_ulong *data)
1894{
1895 env->pc = data[0];
1896}
1880}
1881
1882void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb,
1883 target_ulong *data)
1884{
1885 env->pc = data[0];
1886}