translate.c (5c8f44b7dbdec77eff2ed3e239ea31d649894932) translate.c (faa48d742c2133ec1795d2086be14178c785024a)
1/*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public

--- 646 unchanged lines hidden (view full) ---

655 cpu_R[dc->ra]);
656 if (!dc->rd)
657 tcg_gen_movi_tl(cpu_R[dc->rd], 0);
658}
659
660static void dec_barrel(DisasContext *dc)
661{
662 TCGv t0;
1/*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public

--- 646 unchanged lines hidden (view full) ---

655 cpu_R[dc->ra]);
656 if (!dc->rd)
657 tcg_gen_movi_tl(cpu_R[dc->rd], 0);
658}
659
660static void dec_barrel(DisasContext *dc)
661{
662 TCGv t0;
663 bool s, t;
663 unsigned int imm_w, imm_s;
664 bool s, t, e = false;
664
665 if ((dc->tb_flags & MSR_EE_FLAG)
666 && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
667 && !dc->cpu->cfg.use_barrel) {
668 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
669 t_gen_raise_exception(dc, EXCP_HW_EXCP);
670 return;
671 }
672
665
666 if ((dc->tb_flags & MSR_EE_FLAG)
667 && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
668 && !dc->cpu->cfg.use_barrel) {
669 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
670 t_gen_raise_exception(dc, EXCP_HW_EXCP);
671 return;
672 }
673
674 if (dc->type_b) {
675 /* Insert and extract are only available in immediate mode. */
676 e = extract32(dc->imm, 14, 1);
677 }
673 s = extract32(dc->imm, 10, 1);
674 t = extract32(dc->imm, 9, 1);
678 s = extract32(dc->imm, 10, 1);
679 t = extract32(dc->imm, 9, 1);
680 imm_w = extract32(dc->imm, 6, 5);
681 imm_s = extract32(dc->imm, 0, 5);
675
682
676 LOG_DIS("bs%s%s r%d r%d r%d\n",
683 LOG_DIS("bs%s%s%s r%d r%d r%d\n",
684 e ? "e" : "",
677 s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
678
685 s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
686
679 t0 = tcg_temp_new();
687 if (e) {
688 if (imm_w + imm_s > 32 || imm_w == 0) {
689 /* These inputs have an undefined behavior. */
690 qemu_log_mask(LOG_GUEST_ERROR, "bsefi: Bad input w=%d s=%d\n",
691 imm_w, imm_s);
692 } else {
693 tcg_gen_extract_i32(cpu_R[dc->rd], cpu_R[dc->ra], imm_s, imm_w);
694 }
695 } else {
696 t0 = tcg_temp_new();
680
697
681 tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
682 tcg_gen_andi_tl(t0, t0, 31);
698 tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
699 tcg_gen_andi_tl(t0, t0, 31);
683
700
684 if (s) {
685 tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
686 } else {
687 if (t) {
688 tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
701 if (s) {
702 tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
689 } else {
703 } else {
690 tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
704 if (t) {
705 tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
706 } else {
707 tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
708 }
691 }
709 }
710 tcg_temp_free(t0);
692 }
711 }
693 tcg_temp_free(t0);
694}
695
696static void dec_bit(DisasContext *dc)
697{
698 CPUState *cs = CPU(dc->cpu);
699 TCGv t0;
700 unsigned int op;
701 int mem_index = cpu_mmu_index(&dc->cpu->env, false);

--- 1172 unchanged lines hidden --- 		712}
713
714static void dec_bit(DisasContext *dc)
715{
716 CPUState *cs = CPU(dc->cpu);
717 TCGv t0;
718 unsigned int op;
719 int mem_index = cpu_mmu_index(&dc->cpu->env, false);

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