translate.c (5683750909fb407261b5ad00fed4ad9460ab6845) translate.c (8fc5239e1f8df617147dfe9761dd78291fea78d7)
1/*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public

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321}
322
323static void dec_pattern(DisasContext *dc)
324{
325 unsigned int mode;
326
327 if ((dc->tb_flags & MSR_EE_FLAG)
328 && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1/*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public

--- 312 unchanged lines hidden (view full) ---

321}
322
323static void dec_pattern(DisasContext *dc)
324{
325 unsigned int mode;
326
327 if ((dc->tb_flags & MSR_EE_FLAG)
328 && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
329 && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
329 && !dc->cpu->cfg.use_pcmp_instr) {
330 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
331 t_gen_raise_exception(dc, EXCP_HW_EXCP);
332 }
333
334 mode = dc->opcode & 3;
335 switch (mode) {
336 case 0:
337 /* pcmpbf. */

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757 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
758 t_gen_raise_exception(dc, EXCP_HW_EXCP);
759 return;
760 }
761 break;
762 case 0xe0:
763 if ((dc->tb_flags & MSR_EE_FLAG)
764 && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
330 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
331 t_gen_raise_exception(dc, EXCP_HW_EXCP);
332 }
333
334 mode = dc->opcode & 3;
335 switch (mode) {
336 case 0:
337 /* pcmpbf. */

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757 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
758 t_gen_raise_exception(dc, EXCP_HW_EXCP);
759 return;
760 }
761 break;
762 case 0xe0:
763 if ((dc->tb_flags & MSR_EE_FLAG)
764 && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
765 && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
765 && !dc->cpu->cfg.use_pcmp_instr) {
766 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
767 t_gen_raise_exception(dc, EXCP_HW_EXCP);
768 }
766 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
767 t_gen_raise_exception(dc, EXCP_HW_EXCP);
768 }
769 if (dc->cpu->env.pvr.regs[2] & PVR2_USE_PCMP_INSTR) {
769 if (dc->cpu->cfg.use_pcmp_instr) {
770 tcg_gen_clzi_i32(cpu_R[dc->rd], cpu_R[dc->ra], 32);
771 }
772 break;
773 case 0x1e0:
774 /* swapb */
775 LOG_DIS("swapb r%d r%d\n", dc->rd, dc->ra);
776 tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
777 break;

--- 1094 unchanged lines hidden --- 		770 tcg_gen_clzi_i32(cpu_R[dc->rd], cpu_R[dc->ra], 32);
771 }
772 break;
773 case 0x1e0:
774 /* swapb */
775 LOG_DIS("swapb r%d r%d\n", dc->rd, dc->ra);
776 tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
777 break;

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