translate.c (05a9a6519c9127b5fb0b13481ecc0e72331c8a38) translate.c (f0f7e7f7b284f536389a3c5b67de681055325317)
1/*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public

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454 tcg_temp_free_i64(t);
455}
456
457static void dec_msr(DisasContext *dc)
458{
459 CPUState *cs = CPU(dc->cpu);
460 TCGv_i32 t0, t1;
461 unsigned int sr, rn;
1/*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public

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454 tcg_temp_free_i64(t);
455}
456
457static void dec_msr(DisasContext *dc)
458{
459 CPUState *cs = CPU(dc->cpu);
460 TCGv_i32 t0, t1;
461 unsigned int sr, rn;
462 bool to, clrset, extended;
462 bool to, clrset, extended = false;
463
464 sr = extract32(dc->imm, 0, 14);
465 to = extract32(dc->imm, 14, 1);
466 clrset = extract32(dc->imm, 15, 1) == 0;
467 dc->type_b = 1;
468 if (to) {
469 dc->cpustate_changed = 1;
463
464 sr = extract32(dc->imm, 0, 14);
465 to = extract32(dc->imm, 14, 1);
466 clrset = extract32(dc->imm, 15, 1) == 0;
467 dc->type_b = 1;
468 if (to) {
469 dc->cpustate_changed = 1;
470 extended = extract32(dc->imm, 24, 1);
471 } else {
472 extended = extract32(dc->imm, 19, 1);
473 }
474
470 }
471
472 /* Extended MSRs are only available if addr_size > 32. */
473 if (dc->cpu->cfg.addr_size > 32) {
474 /* The E-bit is encoded differently for To/From MSR. */
475 static const unsigned int e_bit[] = { 19, 24 };
476
477 extended = extract32(dc->imm, e_bit[to], 1);
478 }
479
475 /* msrclr and msrset. */
476 if (clrset) {
477 bool clr = extract32(dc->ir, 16, 1);
478
479 LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
480 dc->rd, dc->imm);
481
482 if (!dc->cpu->cfg.use_msr_instr) {

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511
512 if (trap_userspace(dc, to)) {
513 return;
514 }
515
516#if !defined(CONFIG_USER_ONLY)
517 /* Catch read/writes to the mmu block. */
518 if ((sr & ~0xff) == 0x1000) {
480 /* msrclr and msrset. */
481 if (clrset) {
482 bool clr = extract32(dc->ir, 16, 1);
483
484 LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
485 dc->rd, dc->imm);
486
487 if (!dc->cpu->cfg.use_msr_instr) {

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516
517 if (trap_userspace(dc, to)) {
518 return;
519 }
520
521#if !defined(CONFIG_USER_ONLY)
522 /* Catch read/writes to the mmu block. */
523 if ((sr & ~0xff) == 0x1000) {
524 TCGv_i32 tmp_ext = tcg_const_i32(extended);
519 TCGv_i32 tmp_sr;
520
521 sr &= 7;
522 tmp_sr = tcg_const_i32(sr);
523 LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
524 if (to) {
525 TCGv_i32 tmp_sr;
526
527 sr &= 7;
528 tmp_sr = tcg_const_i32(sr);
529 LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
530 if (to) {
525 gen_helper_mmu_write(cpu_env, tmp_sr, cpu_R[dc->ra]);
531 gen_helper_mmu_write(cpu_env, tmp_ext, tmp_sr, cpu_R[dc->ra]);
526 } else {
532 } else {
527 gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tmp_sr);
533 gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tmp_ext, tmp_sr);
528 }
529 tcg_temp_free_i32(tmp_sr);
534 }
535 tcg_temp_free_i32(tmp_sr);
536 tcg_temp_free_i32(tmp_ext);
530 return;
531 }
532#endif
533
534 if (to) {
535 LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
536 switch (sr) {
537 case 0:

--- 1316 unchanged lines hidden --- 		537 return;
538 }
539#endif
540
541 if (to) {
542 LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
543 switch (sr) {
544 case 0:

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