op_helper.c (78e9caf2f9410c8b90bb6d5a6449c750056c3f8a) | op_helper.c (5a8e01366c5dfe93f608e7d37f385962495d5161) |
---|---|
1/* 2 * Microblaze helper routines. 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>. 5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public --- 161 unchanged lines hidden (view full) --- 170 helper_raise_exception(env, EXCP_HW_EXCP); 171} 172 173static void update_fpu_flags(CPUMBState *env, int flags) 174{ 175 int raise = 0; 176 177 if (flags & float_flag_invalid) { | 1/* 2 * Microblaze helper routines. 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>. 5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public --- 161 unchanged lines hidden (view full) --- 170 helper_raise_exception(env, EXCP_HW_EXCP); 171} 172 173static void update_fpu_flags(CPUMBState *env, int flags) 174{ 175 int raise = 0; 176 177 if (flags & float_flag_invalid) { |
178 env->sregs[SR_FSR] |= FSR_IO; | 178 env->fsr |= FSR_IO; |
179 raise = 1; 180 } 181 if (flags & float_flag_divbyzero) { | 179 raise = 1; 180 } 181 if (flags & float_flag_divbyzero) { |
182 env->sregs[SR_FSR] |= FSR_DZ; | 182 env->fsr |= FSR_DZ; |
183 raise = 1; 184 } 185 if (flags & float_flag_overflow) { | 183 raise = 1; 184 } 185 if (flags & float_flag_overflow) { |
186 env->sregs[SR_FSR] |= FSR_OF; | 186 env->fsr |= FSR_OF; |
187 raise = 1; 188 } 189 if (flags & float_flag_underflow) { | 187 raise = 1; 188 } 189 if (flags & float_flag_underflow) { |
190 env->sregs[SR_FSR] |= FSR_UF; | 190 env->fsr |= FSR_UF; |
191 raise = 1; 192 } 193 if (raise 194 && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK) 195 && (env->msr & MSR_EE)) { 196 raise_fpu_exception(env); 197 } 198} --- 305 unchanged lines hidden --- | 191 raise = 1; 192 } 193 if (raise 194 && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK) 195 && (env->msr & MSR_EE)) { 196 raise_fpu_exception(env); 197 } 198} --- 305 unchanged lines hidden --- |