cpu.c (d1e8e8ecc3d2a1a72504912d671f1cbbac1b06e5) cpu.c (1f5c00cfdb8114c1e3a13426588ceb64f82c9ddb)
1/*
2 * QEMU MicroBlaze CPU
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 * Copyright (c) 2012 SUSE LINUX Products GmbH
7 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
8 *

--- 89 unchanged lines hidden (view full) ---

98static void mb_cpu_reset(CPUState *s)
99{
100 MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
101 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
102 CPUMBState *env = &cpu->env;
103
104 mcc->parent_reset(s);
105
1/*
2 * QEMU MicroBlaze CPU
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 * Copyright (c) 2012 SUSE LINUX Products GmbH
7 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
8 *

--- 89 unchanged lines hidden (view full) ---

98static void mb_cpu_reset(CPUState *s)
99{
100 MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
101 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
102 CPUMBState *env = &cpu->env;
103
104 mcc->parent_reset(s);
105
106 memset(env, 0, offsetof(CPUMBState, pvr));
106 memset(env, 0, offsetof(CPUMBState, end_reset_fields));
107 env->res_addr = RES_ADDR_NONE;
107 env->res_addr = RES_ADDR_NONE;
108 tlb_flush(s, 1);
109
110 /* Disable stack protector. */
111 env->shr = ~0;
112
113 env->sregs[SR_PC] = cpu->cfg.base_vectors;
114
115#if defined(CONFIG_USER_ONLY)
116 /* start in user mode with interrupts enabled. */

--- 176 unchanged lines hidden --- 		108
109 /* Disable stack protector. */
110 env->shr = ~0;
111
112 env->sregs[SR_PC] = cpu->cfg.base_vectors;
113
114#if defined(CONFIG_USER_ONLY)
115 /* start in user mode with interrupts enabled. */

--- 176 unchanged lines hidden ---