vmx.h (1ccda935d4fcc82a4371dc23d660197b0a6b6951) vmx.h (19f703477314a5db09ffc3c0f6be9c45645f8302)
1/*
2 * Copyright (C) 2016 Veertu Inc,
3 * Copyright (C) 2017 Google Inc,
4 * Based on Veertu vddh/vmm/vmx.h
5 *
6 * Interfaces to Hypervisor.framework to read/write X86 registers and VMCS.
7 *
8 * This program is free software; you can redistribute it and/or

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120 int i;
121 uint64_t pdpte[4] = {0, 0, 0, 0};
122 uint64_t efer = rvmcs(vcpu, VMCS_GUEST_IA32_EFER);
123 uint64_t old_cr0 = rvmcs(vcpu, VMCS_GUEST_CR0);
124 uint64_t mask = CR0_PG | CR0_CD | CR0_NW | CR0_NE | CR0_ET;
125
126 if ((cr0 & CR0_PG) && (rvmcs(vcpu, VMCS_GUEST_CR4) & CR4_PAE) &&
127 !(efer & MSR_EFER_LME)) {
1/*
2 * Copyright (C) 2016 Veertu Inc,
3 * Copyright (C) 2017 Google Inc,
4 * Based on Veertu vddh/vmm/vmx.h
5 *
6 * Interfaces to Hypervisor.framework to read/write X86 registers and VMCS.
7 *
8 * This program is free software; you can redistribute it and/or

--- 111 unchanged lines hidden (view full) ---

120 int i;
121 uint64_t pdpte[4] = {0, 0, 0, 0};
122 uint64_t efer = rvmcs(vcpu, VMCS_GUEST_IA32_EFER);
123 uint64_t old_cr0 = rvmcs(vcpu, VMCS_GUEST_CR0);
124 uint64_t mask = CR0_PG | CR0_CD | CR0_NW | CR0_NE | CR0_ET;
125
126 if ((cr0 & CR0_PG) && (rvmcs(vcpu, VMCS_GUEST_CR4) & CR4_PAE) &&
127 !(efer & MSR_EFER_LME)) {
128 address_space_rw(&address_space_memory,
129 rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f,
130 MEMTXATTRS_UNSPECIFIED,
131 pdpte, 32, false);
128 address_space_read(&address_space_memory,
129 rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f,
130 MEMTXATTRS_UNSPECIFIED, pdpte, 32);
132 /* Only set PDPTE when appropriate. */
133 for (i = 0; i < 4; i++) {
134 wvmcs(vcpu, VMCS_GUEST_PDPTE0 + i * 2, pdpte[i]);
135 }
136 }
137
138 wvmcs(vcpu, VMCS_CR0_MASK, mask);
139 wvmcs(vcpu, VMCS_CR0_SHADOW, cr0);

--- 87 unchanged lines hidden --- 		131 /* Only set PDPTE when appropriate. */
132 for (i = 0; i < 4; i++) {
133 wvmcs(vcpu, VMCS_GUEST_PDPTE0 + i * 2, pdpte[i]);
134 }
135 }
136
137 wvmcs(vcpu, VMCS_CR0_MASK, mask);
138 wvmcs(vcpu, VMCS_CR0_SHADOW, cr0);

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