helper.c (a8c611e1133f97c979922f41103f79309339dc27) helper.c (b39466269b9b3c29b0c31c1320aa519f376b750f)
1/*
2 * i386 helpers (without register variable usage)
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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19
20#include "qemu/osdep.h"
21#include "cpu.h"
22#include "exec/exec-all.h"
23#include "sysemu/kvm.h"
24#include "kvm_i386.h"
25#ifndef CONFIG_USER_ONLY
26#include "sysemu/sysemu.h"
1/*
2 * i386 helpers (without register variable usage)
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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19
20#include "qemu/osdep.h"
21#include "cpu.h"
22#include "exec/exec-all.h"
23#include "sysemu/kvm.h"
24#include "kvm_i386.h"
25#ifndef CONFIG_USER_ONLY
26#include "sysemu/sysemu.h"
27#include "sysemu/hw_accel.h"
27#include "monitor/monitor.h"
28#include "hw/i386/apic_internal.h"
29#endif
30
31static void cpu_x86_version(CPUX86State *env, int *family, int *model)
32{
33 int cpuver = env->cpuid_version;
34

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581
582 qemu_log_mask(CPU_LOG_MMU, "A20 update: a20=%d\n", a20_state);
583 /* if the cpu is currently executing code, we must unlink it and
584 all the potentially executing TB */
585 cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
586
587 /* when a20 is changed, all the MMU mappings are invalid, so
588 we must flush everything */
28#include "monitor/monitor.h"
29#include "hw/i386/apic_internal.h"
30#endif
31
32static void cpu_x86_version(CPUX86State *env, int *family, int *model)
33{
34 int cpuver = env->cpuid_version;
35

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582
583 qemu_log_mask(CPU_LOG_MMU, "A20 update: a20=%d\n", a20_state);
584 /* if the cpu is currently executing code, we must unlink it and
585 all the potentially executing TB */
586 cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
587
588 /* when a20 is changed, all the MMU mappings are invalid, so
589 we must flush everything */
589 tlb_flush(cs);
590 tlb_flush(cs, 1);
590 env->a20_mask = ~(1 << 20) | (a20_state << 20);
591 }
592}
593
594void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
595{
596 X86CPU *cpu = x86_env_get_cpu(env);
597 int pe_state;
598
599 qemu_log_mask(CPU_LOG_MMU, "CR0 update: CR0=0x%08x\n", new_cr0);
600 if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
601 (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
591 env->a20_mask = ~(1 << 20) | (a20_state << 20);
592 }
593}
594
595void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
596{
597 X86CPU *cpu = x86_env_get_cpu(env);
598 int pe_state;
599
600 qemu_log_mask(CPU_LOG_MMU, "CR0 update: CR0=0x%08x\n", new_cr0);
601 if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
602 (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
602 tlb_flush(CPU(cpu));
603 tlb_flush(CPU(cpu), 1);
603 }
604
605#ifdef TARGET_X86_64
606 if (!(env->cr[0] & CR0_PG_MASK) && (new_cr0 & CR0_PG_MASK) &&
607 (env->efer & MSR_EFER_LME)) {
608 /* enter in long mode */
609 /* XXX: generate an exception */
610 if (!(env->cr[4] & CR4_PAE_MASK))

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636void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
637{
638 X86CPU *cpu = x86_env_get_cpu(env);
639
640 env->cr[3] = new_cr3;
641 if (env->cr[0] & CR0_PG_MASK) {
642 qemu_log_mask(CPU_LOG_MMU,
643 "CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
604 }
605
606#ifdef TARGET_X86_64
607 if (!(env->cr[0] & CR0_PG_MASK) && (new_cr0 & CR0_PG_MASK) &&
608 (env->efer & MSR_EFER_LME)) {
609 /* enter in long mode */
610 /* XXX: generate an exception */
611 if (!(env->cr[4] & CR4_PAE_MASK))

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637void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
638{
639 X86CPU *cpu = x86_env_get_cpu(env);
640
641 env->cr[3] = new_cr3;
642 if (env->cr[0] & CR0_PG_MASK) {
643 qemu_log_mask(CPU_LOG_MMU,
644 "CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
644 tlb_flush(CPU(cpu));
645 tlb_flush(CPU(cpu), 0);
645 }
646}
647
648void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
649{
650 X86CPU *cpu = x86_env_get_cpu(env);
651 uint32_t hflags;
652
653#if defined(DEBUG_MMU)
654 printf("CR4 update: %08x -> %08x\n", (uint32_t)env->cr[4], new_cr4);
655#endif
656 if ((new_cr4 ^ env->cr[4]) &
657 (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK |
658 CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_LA57_MASK)) {
646 }
647}
648
649void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
650{
651 X86CPU *cpu = x86_env_get_cpu(env);
652 uint32_t hflags;
653
654#if defined(DEBUG_MMU)
655 printf("CR4 update: %08x -> %08x\n", (uint32_t)env->cr[4], new_cr4);
656#endif
657 if ((new_cr4 ^ env->cr[4]) &
658 (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK |
659 CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_LA57_MASK)) {
659 tlb_flush(CPU(cpu));
660 tlb_flush(CPU(cpu), 1);
660 }
661
662 /* Clear bits we're going to recompute. */
663 hflags = env->hflags & ~(HF_OSFXSR_MASK | HF_SMAP_MASK);
664
665 /* SSE handling */
666 if (!(env->features[FEAT_1_EDX] & CPUID_SSE)) {
667 new_cr4 &= ~CR4_OSFXSR_MASK;

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662
663 /* Clear bits we're going to recompute. */
664 hflags = env->hflags & ~(HF_OSFXSR_MASK | HF_SMAP_MASK);
665
666 /* SSE handling */
667 if (!(env->features[FEAT_1_EDX] & CPUID_SSE)) {
668 new_cr4 &= ~CR4_OSFXSR_MASK;

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