translate.c (fa8e3bed3885522260f796ed9d2a17f693c85381) translate.c (af240753331940d0f3f8be6fe625c00fc64c4398)
1/*
2 * HPPA emulation cpu translation for qemu.
3 *
4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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1431 }
1432 tcg_r1 = load_gpr(ctx, a->r1);
1433 tcg_r2 = load_gpr(ctx, a->r2);
1434 do_log(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, fn);
1435 return nullify_end(ctx);
1436}
1437
1438static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1,
1/*
2 * HPPA emulation cpu translation for qemu.
3 *
4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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1431 }
1432 tcg_r1 = load_gpr(ctx, a->r1);
1433 tcg_r2 = load_gpr(ctx, a->r2);
1434 do_log(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, fn);
1435 return nullify_end(ctx);
1436}
1437
1438static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1,
1439 TCGv_reg in2, unsigned cf, bool is_tc,
1439 TCGv_reg in2, unsigned cf, bool d, bool is_tc,
1440 void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg))
1441{
1442 TCGv_reg dest;
1443 DisasCond cond;
1440 void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg))
1441{
1442 TCGv_reg dest;
1443 DisasCond cond;
1444 bool d = false;
1445
1446 if (cf == 0) {
1447 dest = dest_gpr(ctx, rt);
1448 fn(dest, in1, in2);
1449 save_gpr(ctx, rt, dest);
1450 cond_free(&ctx->null_cond);
1451 } else {
1452 dest = tcg_temp_new();

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2767 nullify_over(ctx);
2768 }
2769 tcg_r1 = load_gpr(ctx, a->r1);
2770 tcg_r2 = load_gpr(ctx, a->r2);
2771 do_cmpclr(ctx, a->t, tcg_r1, tcg_r2, a->cf);
2772 return nullify_end(ctx);
2773}
2774
1444
1445 if (cf == 0) {
1446 dest = dest_gpr(ctx, rt);
1447 fn(dest, in1, in2);
1448 save_gpr(ctx, rt, dest);
1449 cond_free(&ctx->null_cond);
1450 } else {
1451 dest = tcg_temp_new();

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2766 nullify_over(ctx);
2767 }
2768 tcg_r1 = load_gpr(ctx, a->r1);
2769 tcg_r2 = load_gpr(ctx, a->r2);
2770 do_cmpclr(ctx, a->t, tcg_r1, tcg_r2, a->cf);
2771 return nullify_end(ctx);
2772}
2773
2775static bool trans_uxor(DisasContext *ctx, arg_rrr_cf *a)
2774static bool trans_uxor(DisasContext *ctx, arg_rrr_cf_d *a)
2776{
2777 TCGv_reg tcg_r1, tcg_r2;
2778
2779 if (a->cf) {
2780 nullify_over(ctx);
2781 }
2782 tcg_r1 = load_gpr(ctx, a->r1);
2783 tcg_r2 = load_gpr(ctx, a->r2);
2775{
2776 TCGv_reg tcg_r1, tcg_r2;
2777
2778 if (a->cf) {
2779 nullify_over(ctx);
2780 }
2781 tcg_r1 = load_gpr(ctx, a->r1);
2782 tcg_r2 = load_gpr(ctx, a->r2);
2784 do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, false, tcg_gen_xor_reg);
2783 do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, false, tcg_gen_xor_reg);
2785 return nullify_end(ctx);
2786}
2787
2784 return nullify_end(ctx);
2785}
2786
2788static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf *a, bool is_tc)
2787static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tc)
2789{
2790 TCGv_reg tcg_r1, tcg_r2, tmp;
2791
2792 if (a->cf) {
2793 nullify_over(ctx);
2794 }
2795 tcg_r1 = load_gpr(ctx, a->r1);
2796 tcg_r2 = load_gpr(ctx, a->r2);
2797 tmp = tcg_temp_new();
2798 tcg_gen_not_reg(tmp, tcg_r2);
2788{
2789 TCGv_reg tcg_r1, tcg_r2, tmp;
2790
2791 if (a->cf) {
2792 nullify_over(ctx);
2793 }
2794 tcg_r1 = load_gpr(ctx, a->r1);
2795 tcg_r2 = load_gpr(ctx, a->r2);
2796 tmp = tcg_temp_new();
2797 tcg_gen_not_reg(tmp, tcg_r2);
2799 do_unit(ctx, a->t, tcg_r1, tmp, a->cf, is_tc, tcg_gen_add_reg);
2798 do_unit(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, tcg_gen_add_reg);
2800 return nullify_end(ctx);
2801}
2802
2799 return nullify_end(ctx);
2800}
2801
2803static bool trans_uaddcm(DisasContext *ctx, arg_rrr_cf *a)
2802static bool trans_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a)
2804{
2805 return do_uaddcm(ctx, a, false);
2806}
2807
2803{
2804 return do_uaddcm(ctx, a, false);
2805}
2806
2808static bool trans_uaddcm_tc(DisasContext *ctx, arg_rrr_cf *a)
2807static bool trans_uaddcm_tc(DisasContext *ctx, arg_rrr_cf_d *a)
2809{
2810 return do_uaddcm(ctx, a, true);
2811}
2812
2808{
2809 return do_uaddcm(ctx, a, true);
2810}
2811
2813static bool do_dcor(DisasContext *ctx, arg_rr_cf *a, bool is_i)
2812static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a, bool is_i)
2814{
2815 TCGv_reg tmp;
2816
2817 nullify_over(ctx);
2818
2819 tmp = tcg_temp_new();
2820 tcg_gen_shri_reg(tmp, cpu_psw_cb, 3);
2821 if (!is_i) {
2822 tcg_gen_not_reg(tmp, tmp);
2823 }
2813{
2814 TCGv_reg tmp;
2815
2816 nullify_over(ctx);
2817
2818 tmp = tcg_temp_new();
2819 tcg_gen_shri_reg(tmp, cpu_psw_cb, 3);
2820 if (!is_i) {
2821 tcg_gen_not_reg(tmp, tmp);
2822 }
2824 tcg_gen_andi_reg(tmp, tmp, 0x11111111);
2823 tcg_gen_andi_reg(tmp, tmp, (target_ureg)0x1111111111111111ull);
2825 tcg_gen_muli_reg(tmp, tmp, 6);
2824 tcg_gen_muli_reg(tmp, tmp, 6);
2826 do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, false,
2825 do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, a->d, false,
2827 is_i ? tcg_gen_add_reg : tcg_gen_sub_reg);
2828 return nullify_end(ctx);
2829}
2830
2826 is_i ? tcg_gen_add_reg : tcg_gen_sub_reg);
2827 return nullify_end(ctx);
2828}
2829
2831static bool trans_dcor(DisasContext *ctx, arg_rr_cf *a)
2830static bool trans_dcor(DisasContext *ctx, arg_rr_cf_d *a)
2832{
2833 return do_dcor(ctx, a, false);
2834}
2835
2831{
2832 return do_dcor(ctx, a, false);
2833}
2834
2836static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf *a)
2835static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf_d *a)
2837{
2838 return do_dcor(ctx, a, true);
2839}
2840
2841static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a)
2842{
2843 TCGv_reg dest, add1, add2, addc, zero, in1, in2;
2844 TCGv_reg cout;

--- 1562 unchanged lines hidden --- 		2836{
2837 return do_dcor(ctx, a, true);
2838}
2839
2840static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a)
2841{
2842 TCGv_reg dest, add1, add2, addc, zero, in1, in2;
2843 TCGv_reg cout;

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