translate.c (f2cfa1229e539ee1bb1822912075cf25538ad6b9) translate.c (14776ab5a12972ea439c7fb2203a4c15a09094b4)
1/*
2 * HPPA emulation cpu translation for qemu.
3 *
4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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1495
1496/* Emit a memory load. The modify parameter should be
1497 * < 0 for pre-modify,
1498 * > 0 for post-modify,
1499 * = 0 for no base register update.
1500 */
1501static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb,
1502 unsigned rx, int scale, target_sreg disp,
1/*
2 * HPPA emulation cpu translation for qemu.
3 *
4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

--- 1486 unchanged lines hidden (view full) ---

1495
1496/* Emit a memory load. The modify parameter should be
1497 * < 0 for pre-modify,
1498 * > 0 for post-modify,
1499 * = 0 for no base register update.
1500 */
1501static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb,
1502 unsigned rx, int scale, target_sreg disp,
1503 unsigned sp, int modify, TCGMemOp mop)
1503 unsigned sp, int modify, MemOp mop)
1504{
1505 TCGv_reg ofs;
1506 TCGv_tl addr;
1507
1508 /* Caller uses nullify_over/nullify_end. */
1509 assert(ctx->null_cond.c == TCG_COND_NEVER);
1510
1511 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
1512 ctx->mmu_idx == MMU_PHYS_IDX);
1513 tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop);
1514 if (modify) {
1515 save_gpr(ctx, rb, ofs);
1516 }
1517}
1518
1519static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb,
1520 unsigned rx, int scale, target_sreg disp,
1504{
1505 TCGv_reg ofs;
1506 TCGv_tl addr;
1507
1508 /* Caller uses nullify_over/nullify_end. */
1509 assert(ctx->null_cond.c == TCG_COND_NEVER);
1510
1511 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
1512 ctx->mmu_idx == MMU_PHYS_IDX);
1513 tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop);
1514 if (modify) {
1515 save_gpr(ctx, rb, ofs);
1516 }
1517}
1518
1519static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb,
1520 unsigned rx, int scale, target_sreg disp,
1521 unsigned sp, int modify, TCGMemOp mop)
1521 unsigned sp, int modify, MemOp mop)
1522{
1523 TCGv_reg ofs;
1524 TCGv_tl addr;
1525
1526 /* Caller uses nullify_over/nullify_end. */
1527 assert(ctx->null_cond.c == TCG_COND_NEVER);
1528
1529 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
1530 ctx->mmu_idx == MMU_PHYS_IDX);
1531 tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop);
1532 if (modify) {
1533 save_gpr(ctx, rb, ofs);
1534 }
1535}
1536
1537static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb,
1538 unsigned rx, int scale, target_sreg disp,
1522{
1523 TCGv_reg ofs;
1524 TCGv_tl addr;
1525
1526 /* Caller uses nullify_over/nullify_end. */
1527 assert(ctx->null_cond.c == TCG_COND_NEVER);
1528
1529 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
1530 ctx->mmu_idx == MMU_PHYS_IDX);
1531 tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop);
1532 if (modify) {
1533 save_gpr(ctx, rb, ofs);
1534 }
1535}
1536
1537static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb,
1538 unsigned rx, int scale, target_sreg disp,
1539 unsigned sp, int modify, TCGMemOp mop)
1539 unsigned sp, int modify, MemOp mop)
1540{
1541 TCGv_reg ofs;
1542 TCGv_tl addr;
1543
1544 /* Caller uses nullify_over/nullify_end. */
1545 assert(ctx->null_cond.c == TCG_COND_NEVER);
1546
1547 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
1548 ctx->mmu_idx == MMU_PHYS_IDX);
1549 tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop);
1550 if (modify) {
1551 save_gpr(ctx, rb, ofs);
1552 }
1553}
1554
1555static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb,
1556 unsigned rx, int scale, target_sreg disp,
1540{
1541 TCGv_reg ofs;
1542 TCGv_tl addr;
1543
1544 /* Caller uses nullify_over/nullify_end. */
1545 assert(ctx->null_cond.c == TCG_COND_NEVER);
1546
1547 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
1548 ctx->mmu_idx == MMU_PHYS_IDX);
1549 tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop);
1550 if (modify) {
1551 save_gpr(ctx, rb, ofs);
1552 }
1553}
1554
1555static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb,
1556 unsigned rx, int scale, target_sreg disp,
1557 unsigned sp, int modify, TCGMemOp mop)
1557 unsigned sp, int modify, MemOp mop)
1558{
1559 TCGv_reg ofs;
1560 TCGv_tl addr;
1561
1562 /* Caller uses nullify_over/nullify_end. */
1563 assert(ctx->null_cond.c == TCG_COND_NEVER);
1564
1565 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,

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1575#define do_store_reg do_store_64
1576#else
1577#define do_load_reg do_load_32
1578#define do_store_reg do_store_32
1579#endif
1580
1581static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb,
1582 unsigned rx, int scale, target_sreg disp,
1558{
1559 TCGv_reg ofs;
1560 TCGv_tl addr;
1561
1562 /* Caller uses nullify_over/nullify_end. */
1563 assert(ctx->null_cond.c == TCG_COND_NEVER);
1564
1565 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,

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1575#define do_store_reg do_store_64
1576#else
1577#define do_load_reg do_load_32
1578#define do_store_reg do_store_32
1579#endif
1580
1581static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb,
1582 unsigned rx, int scale, target_sreg disp,
1583 unsigned sp, int modify, TCGMemOp mop)
1583 unsigned sp, int modify, MemOp mop)
1584{
1585 TCGv_reg dest;
1586
1587 nullify_over(ctx);
1588
1589 if (modify == 0) {
1590 /* No base register update. */
1591 dest = dest_gpr(ctx, rt);

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1648static bool trans_fldd(DisasContext *ctx, arg_ldst *a)
1649{
1650 return do_floadd(ctx, a->t, a->b, a->x, a->scale ? 3 : 0,
1651 a->disp, a->sp, a->m);
1652}
1653
1654static bool do_store(DisasContext *ctx, unsigned rt, unsigned rb,
1655 target_sreg disp, unsigned sp,
1584{
1585 TCGv_reg dest;
1586
1587 nullify_over(ctx);
1588
1589 if (modify == 0) {
1590 /* No base register update. */
1591 dest = dest_gpr(ctx, rt);

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1648static bool trans_fldd(DisasContext *ctx, arg_ldst *a)
1649{
1650 return do_floadd(ctx, a->t, a->b, a->x, a->scale ? 3 : 0,
1651 a->disp, a->sp, a->m);
1652}
1653
1654static bool do_store(DisasContext *ctx, unsigned rt, unsigned rb,
1655 target_sreg disp, unsigned sp,
1656 int modify, TCGMemOp mop)
1656 int modify, MemOp mop)
1657{
1658 nullify_over(ctx);
1659 do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, sp, modify, mop);
1660 return nullify_end(ctx);
1661}
1662
1663static bool do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb,
1664 unsigned rx, int scale, target_sreg disp,

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2934static bool trans_st(DisasContext *ctx, arg_ldst *a)
2935{
2936 assert(a->x == 0 && a->scale == 0);
2937 return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE);
2938}
2939
2940static bool trans_ldc(DisasContext *ctx, arg_ldst *a)
2941{
1657{
1658 nullify_over(ctx);
1659 do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, sp, modify, mop);
1660 return nullify_end(ctx);
1661}
1662
1663static bool do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb,
1664 unsigned rx, int scale, target_sreg disp,

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2934static bool trans_st(DisasContext *ctx, arg_ldst *a)
2935{
2936 assert(a->x == 0 && a->scale == 0);
2937 return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE);
2938}
2939
2940static bool trans_ldc(DisasContext *ctx, arg_ldst *a)
2941{
2942 TCGMemOp mop = MO_TEUL | MO_ALIGN_16 | a->size;
2942 MemOp mop = MO_TEUL | MO_ALIGN_16 | a->size;
2943 TCGv_reg zero, dest, ofs;
2944 TCGv_tl addr;
2945
2946 nullify_over(ctx);
2947
2948 if (a->m) {
2949 /* Base register modification. Make sure if RT == RB,
2950 we see the result of the load. */

--- 1435 unchanged lines hidden --- 		2943 TCGv_reg zero, dest, ofs;
2944 TCGv_tl addr;
2945
2946 nullify_over(ctx);
2947
2948 if (a->m) {
2949 /* Base register modification. Make sure if RT == RB,
2950 we see the result of the load. */

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