translate.c (c919bc65c54433420eecf8dc918ed6bcfeab40bf) translate.c (24638bd17df4bdd7d54634dd5f6a5e8ec1282dc8)
1/*
2 * HPPA emulation cpu translation for qemu.
3 *
4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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39typedef struct DisasCond {
40 TCGCond c;
41 TCGv_i64 a0, a1;
42} DisasCond;
43
44typedef struct DisasContext {
45 DisasContextBase base;
46 CPUState *cs;
1/*
2 * HPPA emulation cpu translation for qemu.
3 *
4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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39typedef struct DisasCond {
40 TCGCond c;
41 TCGv_i64 a0, a1;
42} DisasCond;
43
44typedef struct DisasContext {
45 DisasContextBase base;
46 CPUState *cs;
47 TCGOp *insn_start;
48
49 uint64_t iaoq_f;
50 uint64_t iaoq_b;
51 uint64_t iaoq_n;
52 TCGv_i64 iaoq_n_var;
53
54 DisasCond null_cond;
55 TCGLabel *null_lab;
56
57 TCGv_i64 zero;
58
59 uint32_t insn;
60 uint32_t tb_flags;
61 int mmu_idx;
62 int privilege;
63 bool psw_n_nonzero;
64 bool is_pa20;
47
48 uint64_t iaoq_f;
49 uint64_t iaoq_b;
50 uint64_t iaoq_n;
51 TCGv_i64 iaoq_n_var;
52
53 DisasCond null_cond;
54 TCGLabel *null_lab;
55
56 TCGv_i64 zero;
57
58 uint32_t insn;
59 uint32_t tb_flags;
60 int mmu_idx;
61 int privilege;
62 bool psw_n_nonzero;
63 bool is_pa20;
64 bool insn_start_updated;
65
66#ifdef CONFIG_USER_ONLY
67 MemOp unalign;
68#endif
69} DisasContext;
70
71#ifdef CONFIG_USER_ONLY
72#define UNALIGN(C) (C)->unalign

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295 "iasq_f");
296 cpu_iasq_b = tcg_global_mem_new_i64(tcg_env,
297 offsetof(CPUHPPAState, iasq_b),
298 "iasq_b");
299}
300
301static void set_insn_breg(DisasContext *ctx, int breg)
302{
65
66#ifdef CONFIG_USER_ONLY
67 MemOp unalign;
68#endif
69} DisasContext;
70
71#ifdef CONFIG_USER_ONLY
72#define UNALIGN(C) (C)->unalign

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295 "iasq_f");
296 cpu_iasq_b = tcg_global_mem_new_i64(tcg_env,
297 offsetof(CPUHPPAState, iasq_b),
298 "iasq_b");
299}
300
301static void set_insn_breg(DisasContext *ctx, int breg)
302{
303 assert(ctx->insn_start != NULL);
304 tcg_set_insn_start_param(ctx->insn_start, 2, breg);
305 ctx->insn_start = NULL;
303 assert(!ctx->insn_start_updated);
304 ctx->insn_start_updated = true;
305 tcg_set_insn_start_param(ctx->base.insn_start, 2, breg);
306}
307
308static DisasCond cond_make_f(void)
309{
310 return (DisasCond){
311 .c = TCG_COND_NEVER,
312 .a0 = NULL,
313 .a1 = NULL,

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4689 ctx->null_lab = NULL;
4690}
4691
4692static void hppa_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
4693{
4694 DisasContext *ctx = container_of(dcbase, DisasContext, base);
4695
4696 tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b, 0);
306}
307
308static DisasCond cond_make_f(void)
309{
310 return (DisasCond){
311 .c = TCG_COND_NEVER,
312 .a0 = NULL,
313 .a1 = NULL,

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4689 ctx->null_lab = NULL;
4690}
4691
4692static void hppa_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
4693{
4694 DisasContext *ctx = container_of(dcbase, DisasContext, base);
4695
4696 tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b, 0);
4697 ctx->insn_start = tcg_last_op();
4697 ctx->insn_start_updated = false;
4698}
4699
4700static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
4701{
4702 DisasContext *ctx = container_of(dcbase, DisasContext, base);
4703 CPUHPPAState *env = cpu_env(cs);
4704 DisasJumpType ret;
4705

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4699
4700static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
4701{
4702 DisasContext *ctx = container_of(dcbase, DisasContext, base);
4703 CPUHPPAState *env = cpu_env(cs);
4704 DisasJumpType ret;
4705

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