translate.c (7f221b0706f7ab8359cb9008650dc7370238839c) translate.c (f49b3537cb28b98284f6ce893ef7240a3cacded3)
1/*
2 * HPPA emulation cpu translation for qemu.
3 *
4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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650}
651
652/* Mark the end of an instruction that may have been nullified.
653 This is the pair to nullify_over. */
654static DisasJumpType nullify_end(DisasContext *ctx, DisasJumpType status)
655{
656 TCGLabel *null_lab = ctx->null_lab;
657
1/*
2 * HPPA emulation cpu translation for qemu.
3 *
4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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650}
651
652/* Mark the end of an instruction that may have been nullified.
653 This is the pair to nullify_over. */
654static DisasJumpType nullify_end(DisasContext *ctx, DisasJumpType status)
655{
656 TCGLabel *null_lab = ctx->null_lab;
657
658 /* For NEXT, NORETURN, STALE, we can easily continue (or exit).
659 For UPDATED, we cannot update on the nullified path. */
660 assert(status != DISAS_IAQ_N_UPDATED);
661
658 if (likely(null_lab == NULL)) {
659 /* The current insn wasn't conditional or handled the condition
660 applied to it without a branch, so the (new) setting of
661 NULL_COND can be applied directly to the next insn. */
662 return status;
663 }
664 ctx->null_lab = NULL;
665

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671 /* The insn that we just executed is itself nullifying the next
672 instruction. Store the condition in the PSW[N] global.
673 We asserted PSW[N] = 0 in nullify_over, so that after the
674 label we have the proper value in place. */
675 nullify_save(ctx);
676 gen_set_label(null_lab);
677 ctx->null_cond = cond_make_n();
678 }
662 if (likely(null_lab == NULL)) {
663 /* The current insn wasn't conditional or handled the condition
664 applied to it without a branch, so the (new) setting of
665 NULL_COND can be applied directly to the next insn. */
666 return status;
667 }
668 ctx->null_lab = NULL;
669

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675 /* The insn that we just executed is itself nullifying the next
676 instruction. Store the condition in the PSW[N] global.
677 We asserted PSW[N] = 0 in nullify_over, so that after the
678 label we have the proper value in place. */
679 nullify_save(ctx);
680 gen_set_label(null_lab);
681 ctx->null_cond = cond_make_n();
682 }
679
680 assert(status != DISAS_NORETURN && status != DISAS_IAQ_N_UPDATED);
681 if (status == DISAS_NORETURN) {
682 status = DISAS_NEXT;
683 }
684 return status;
685}
686
687static void copy_iaoq_entry(TCGv_reg dest, target_ureg ival, TCGv_reg vval)
688{

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2148
2149 reg = load_gpr(ctx, rr);
2150 tmp = get_temp(ctx);
2151 gen_helper_swap_system_mask(tmp, cpu_env, reg);
2152
2153 /* Exit the TB to recognize new interrupts. */
2154 return nullify_end(ctx, DISAS_IAQ_N_STALE_EXIT);
2155}
683 if (status == DISAS_NORETURN) {
684 status = DISAS_NEXT;
685 }
686 return status;
687}
688
689static void copy_iaoq_entry(TCGv_reg dest, target_ureg ival, TCGv_reg vval)
690{

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2150
2151 reg = load_gpr(ctx, rr);
2152 tmp = get_temp(ctx);
2153 gen_helper_swap_system_mask(tmp, cpu_env, reg);
2154
2155 /* Exit the TB to recognize new interrupts. */
2156 return nullify_end(ctx, DISAS_IAQ_N_STALE_EXIT);
2157}
2158
2159static DisasJumpType trans_rfi(DisasContext *ctx, uint32_t insn,
2160 const DisasInsn *di)
2161{
2162 unsigned comp = extract32(insn, 5, 4);
2163
2164 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
2165 nullify_over(ctx);
2166
2167 if (comp == 5) {
2168 gen_helper_rfi_r(cpu_env);
2169 } else {
2170 gen_helper_rfi(cpu_env);
2171 }
2172 if (ctx->base.singlestep_enabled) {
2173 gen_excp_1(EXCP_DEBUG);
2174 } else {
2175 tcg_gen_exit_tb(0);
2176 }
2177
2178 /* Exit the TB to recognize new interrupts. */
2179 return nullify_end(ctx, DISAS_NORETURN);
2180}
2156#endif /* !CONFIG_USER_ONLY */
2157
2158static const DisasInsn table_system[] = {
2159 { 0x00000000u, 0xfc001fe0u, trans_break },
2160 { 0x00001820u, 0xffe01fffu, trans_mtsp },
2161 { 0x00001840u, 0xfc00ffffu, trans_mtctl },
2162 { 0x016018c0u, 0xffe0ffffu, trans_mtsarcm },
2163 { 0x000014a0u, 0xffffffe0u, trans_mfia },
2164 { 0x000004a0u, 0xffff1fe0u, trans_mfsp },
2165 { 0x000008a0u, 0xfc1fbfe0u, trans_mfctl },
2166 { 0x00000400u, 0xffffffffu, trans_sync },
2167 { 0x000010a0u, 0xfc1f3fe0u, trans_ldsid },
2168#ifndef CONFIG_USER_ONLY
2169 { 0x00000e60u, 0xfc00ffe0u, trans_rsm },
2170 { 0x00000d60u, 0xfc00ffe0u, trans_ssm },
2171 { 0x00001860u, 0xffe0ffffu, trans_mtsm },
2181#endif /* !CONFIG_USER_ONLY */
2182
2183static const DisasInsn table_system[] = {
2184 { 0x00000000u, 0xfc001fe0u, trans_break },
2185 { 0x00001820u, 0xffe01fffu, trans_mtsp },
2186 { 0x00001840u, 0xfc00ffffu, trans_mtctl },
2187 { 0x016018c0u, 0xffe0ffffu, trans_mtsarcm },
2188 { 0x000014a0u, 0xffffffe0u, trans_mfia },
2189 { 0x000004a0u, 0xffff1fe0u, trans_mfsp },
2190 { 0x000008a0u, 0xfc1fbfe0u, trans_mfctl },
2191 { 0x00000400u, 0xffffffffu, trans_sync },
2192 { 0x000010a0u, 0xfc1f3fe0u, trans_ldsid },
2193#ifndef CONFIG_USER_ONLY
2194 { 0x00000e60u, 0xfc00ffe0u, trans_rsm },
2195 { 0x00000d60u, 0xfc00ffe0u, trans_ssm },
2196 { 0x00001860u, 0xffe0ffffu, trans_mtsm },
2197 { 0x00000c00u, 0xfffffe1fu, trans_rfi },
2172#endif
2173};
2174
2175static DisasJumpType trans_base_idx_mod(DisasContext *ctx, uint32_t insn,
2176 const DisasInsn *di)
2177{
2178 unsigned rb = extract32(insn, 21, 5);
2179 unsigned rx = extract32(insn, 16, 5);

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2199};
2200
2201static DisasJumpType trans_base_idx_mod(DisasContext *ctx, uint32_t insn,
2202 const DisasInsn *di)
2203{
2204 unsigned rb = extract32(insn, 21, 5);
2205 unsigned rx = extract32(insn, 16, 5);

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