translate.c (25460fc5a71ef2bf6679d263e16f86ed7bb341a5) translate.c (8577f354792414a2b24ef72c64730ed0f6bb071e)
1/*
2 * HPPA emulation cpu translation for qemu.
3 *
4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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2509 gen_helper_probe(dest, tcg_env, addr, level, want);
2510
2511 save_gpr(ctx, a->t, dest);
2512 return nullify_end(ctx);
2513}
2514
2515static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlbx *a)
2516{
1/*
2 * HPPA emulation cpu translation for qemu.
3 *
4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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2509 gen_helper_probe(dest, tcg_env, addr, level, want);
2510
2511 save_gpr(ctx, a->t, dest);
2512 return nullify_end(ctx);
2513}
2514
2515static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlbx *a)
2516{
2517 if (ctx->is_pa20) {
2518 return false;
2519 }
2517 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
2518#ifndef CONFIG_USER_ONLY
2519 TCGv_tl addr;
2520 TCGv_reg ofs, reg;
2521
2522 nullify_over(ctx);
2523
2524 form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false);
2525 reg = load_gpr(ctx, a->r);
2526 if (a->addr) {
2520 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
2521#ifndef CONFIG_USER_ONLY
2522 TCGv_tl addr;
2523 TCGv_reg ofs, reg;
2524
2525 nullify_over(ctx);
2526
2527 form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false);
2528 reg = load_gpr(ctx, a->r);
2529 if (a->addr) {
2527 gen_helper_itlba(tcg_env, addr, reg);
2530 gen_helper_itlba_pa11(tcg_env, addr, reg);
2528 } else {
2531 } else {
2529 gen_helper_itlbp(tcg_env, addr, reg);
2532 gen_helper_itlbp_pa11(tcg_env, addr, reg);
2530 }
2531
2532 /* Exit TB for TLB change if mmu is enabled. */
2533 if (ctx->tb_flags & PSW_C) {
2534 ctx->base.is_jmp = DISAS_IAQ_N_STALE;
2535 }
2536 return nullify_end(ctx);
2537#endif

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2567/*
2568 * Implement the pcxl and pcxl2 Fast TLB Insert instructions.
2569 * See
2570 * https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf
2571 * page 13-9 (195/206)
2572 */
2573static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a)
2574{
2533 }
2534
2535 /* Exit TB for TLB change if mmu is enabled. */
2536 if (ctx->tb_flags & PSW_C) {
2537 ctx->base.is_jmp = DISAS_IAQ_N_STALE;
2538 }
2539 return nullify_end(ctx);
2540#endif

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2570/*
2571 * Implement the pcxl and pcxl2 Fast TLB Insert instructions.
2572 * See
2573 * https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf
2574 * page 13-9 (195/206)
2575 */
2576static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a)
2577{
2578 if (ctx->is_pa20) {
2579 return false;
2580 }
2575 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
2576#ifndef CONFIG_USER_ONLY
2577 TCGv_tl addr, atl, stl;
2578 TCGv_reg reg;
2579
2580 nullify_over(ctx);
2581
2582 /*
2583 * FIXME:
2584 * if (not (pcxl or pcxl2))
2585 * return gen_illegal(ctx);
2581 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
2582#ifndef CONFIG_USER_ONLY
2583 TCGv_tl addr, atl, stl;
2584 TCGv_reg reg;
2585
2586 nullify_over(ctx);
2587
2588 /*
2589 * FIXME:
2590 * if (not (pcxl or pcxl2))
2591 * return gen_illegal(ctx);
2586 *
2587 * Note for future: these are 32-bit systems; no hppa64.
2588 */
2589
2590 atl = tcg_temp_new_tl();
2591 stl = tcg_temp_new_tl();
2592 addr = tcg_temp_new_tl();
2593
2594 tcg_gen_ld32u_i64(stl, tcg_env,
2595 a->data ? offsetof(CPUHPPAState, cr[CR_ISR])
2596 : offsetof(CPUHPPAState, cr[CR_IIASQ]));
2597 tcg_gen_ld32u_i64(atl, tcg_env,
2598 a->data ? offsetof(CPUHPPAState, cr[CR_IOR])
2599 : offsetof(CPUHPPAState, cr[CR_IIAOQ]));
2600 tcg_gen_shli_i64(stl, stl, 32);
2601 tcg_gen_or_tl(addr, atl, stl);
2602
2603 reg = load_gpr(ctx, a->r);
2604 if (a->addr) {
2592 */
2593
2594 atl = tcg_temp_new_tl();
2595 stl = tcg_temp_new_tl();
2596 addr = tcg_temp_new_tl();
2597
2598 tcg_gen_ld32u_i64(stl, tcg_env,
2599 a->data ? offsetof(CPUHPPAState, cr[CR_ISR])
2600 : offsetof(CPUHPPAState, cr[CR_IIASQ]));
2601 tcg_gen_ld32u_i64(atl, tcg_env,
2602 a->data ? offsetof(CPUHPPAState, cr[CR_IOR])
2603 : offsetof(CPUHPPAState, cr[CR_IIAOQ]));
2604 tcg_gen_shli_i64(stl, stl, 32);
2605 tcg_gen_or_tl(addr, atl, stl);
2606
2607 reg = load_gpr(ctx, a->r);
2608 if (a->addr) {
2605 gen_helper_itlba(tcg_env, addr, reg);
2609 gen_helper_itlba_pa11(tcg_env, addr, reg);
2606 } else {
2610 } else {
2607 gen_helper_itlbp(tcg_env, addr, reg);
2611 gen_helper_itlbp_pa11(tcg_env, addr, reg);
2608 }
2609
2610 /* Exit TB for TLB change if mmu is enabled. */
2611 if (ctx->tb_flags & PSW_C) {
2612 ctx->base.is_jmp = DISAS_IAQ_N_STALE;
2613 }
2614 return nullify_end(ctx);
2615#endif
2616}
2617
2612 }
2613
2614 /* Exit TB for TLB change if mmu is enabled. */
2615 if (ctx->tb_flags & PSW_C) {
2616 ctx->base.is_jmp = DISAS_IAQ_N_STALE;
2617 }
2618 return nullify_end(ctx);
2619#endif
2620}
2621
2622static bool trans_ixtlbt(DisasContext *ctx, arg_ixtlbt *a)
2623{
2624 if (!ctx->is_pa20) {
2625 return false;
2626 }
2627 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
2628#ifndef CONFIG_USER_ONLY
2629 nullify_over(ctx);
2630 {
2631 TCGv_i64 src1 = load_gpr(ctx, a->r1);
2632 TCGv_i64 src2 = load_gpr(ctx, a->r2);
2633
2634 if (a->data) {
2635 gen_helper_idtlbt_pa20(tcg_env, src1, src2);
2636 } else {
2637 gen_helper_iitlbt_pa20(tcg_env, src1, src2);
2638 }
2639 }
2640 /* Exit TB for TLB change if mmu is enabled. */
2641 if (ctx->tb_flags & PSW_C) {
2642 ctx->base.is_jmp = DISAS_IAQ_N_STALE;
2643 }
2644 return nullify_end(ctx);
2645#endif
2646}
2647
2618static bool trans_lpa(DisasContext *ctx, arg_ldst *a)
2619{
2620 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
2621#ifndef CONFIG_USER_ONLY
2622 TCGv_tl vaddr;
2623 TCGv_reg ofs, paddr;
2624
2625 nullify_over(ctx);

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2648static bool trans_lpa(DisasContext *ctx, arg_ldst *a)
2649{
2650 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
2651#ifndef CONFIG_USER_ONLY
2652 TCGv_tl vaddr;
2653 TCGv_reg ofs, paddr;
2654
2655 nullify_over(ctx);

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