| insns.decode (fa8e3bed3885522260f796ed9d2a17f693c85381) | insns.decode (af240753331940d0f3f8be6fe625c00fc64c4398) |
|---|---|
| 1# 2# HPPA instruction decode definitions. 3# 4# Copyright (c) 2018 Richard Henderson <rth@twiddle.net> 5# 6# This library is free software; you can redistribute it and/or 7# modify it under the terms of the GNU Lesser General Public 8# License as published by the Free Software Foundation; either --- 45 unchanged lines hidden (view full) --- 54 55#### 56# Argument set definitions 57#### 58 59# All insns that need to form a virtual address should use this set. 60&ldst t b x disp sp m scale size 61 | 1# 2# HPPA instruction decode definitions. 3# 4# Copyright (c) 2018 Richard Henderson <rth@twiddle.net> 5# 6# This library is free software; you can redistribute it and/or 7# modify it under the terms of the GNU Lesser General Public 8# License as published by the Free Software Foundation; either --- 45 unchanged lines hidden (view full) --- 54 55#### 56# Argument set definitions 57#### 58 59# All insns that need to form a virtual address should use this set. 60&ldst t b x disp sp m scale size 61 |
| 62&rr_cf t r cf | 62&rr_cf_d t r cf d |
| 63&rrr_cf t r1 r2 cf 64&rrr_cf_d t r1 r2 cf d 65&rrr_cf_sh t r1 r2 cf sh 66&rri_cf t r i cf 67 68&rrb_c_f disp n c f r1 r2 69&rib_c_f disp n c f r i 70 71#### 72# Format definitions 73#### 74 | 63&rrr_cf t r1 r2 cf 64&rrr_cf_d t r1 r2 cf d 65&rrr_cf_sh t r1 r2 cf sh 66&rri_cf t r i cf 67 68&rrb_c_f disp n c f r1 r2 69&rib_c_f disp n c f r i 70 71#### 72# Format definitions 73#### 74 |
| 75@rr_cf ...... r:5 ..... cf:4 ....... t:5 &rr_cf | 75@rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d |
| 76@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf 77@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d 78@rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh 79@rrr_cf_sh0 ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf_sh sh=0 80@rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11 81 82@rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \ 83 &rrb_c_f disp=%assemble_12 --- 67 unchanged lines hidden (view full) --- 151#### 152# Arith/Log 153#### 154 155andcm 000010 ..... ..... .... 000000 . ..... @rrr_cf_d 156and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d 157or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d 158xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d | 76@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf 77@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d 78@rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh 79@rrr_cf_sh0 ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf_sh sh=0 80@rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11 81 82@rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \ 83 &rrb_c_f disp=%assemble_12 --- 67 unchanged lines hidden (view full) --- 151#### 152# Arith/Log 153#### 154 155andcm 000010 ..... ..... .... 000000 . ..... @rrr_cf_d 156and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d 157or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d 158xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d |
| 159uxor 000010 ..... ..... .... 001110 0 ..... @rrr_cf | 159uxor 000010 ..... ..... .... 001110 . ..... @rrr_cf_d |
| 160ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf 161cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf | 160ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf 161cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf |
| 162uaddcm 000010 ..... ..... .... 100110 0 ..... @rrr_cf 163uaddcm_tc 000010 ..... ..... .... 100111 0 ..... @rrr_cf 164dcor 000010 ..... 00000 .... 101110 0 ..... @rr_cf 165dcor_i 000010 ..... 00000 .... 101111 0 ..... @rr_cf | 162uaddcm 000010 ..... ..... .... 100110 . ..... @rrr_cf_d 163uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d 164dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d 165dcor_i 000010 ..... 00000 .... 101111 . ..... @rr_cf_d |
| 166 167add 000010 ..... ..... .... 0110.. - ..... @rrr_cf_sh 168add_l 000010 ..... ..... .... 1010.. 0 ..... @rrr_cf_sh 169add_tsv 000010 ..... ..... .... 1110.. 0 ..... @rrr_cf_sh 170add_c 000010 ..... ..... .... 011100 0 ..... @rrr_cf_sh0 171add_c_tsv 000010 ..... ..... .... 111100 0 ..... @rrr_cf_sh0 172 173sub 000010 ..... ..... .... 010000 - ..... @rrr_cf --- 360 unchanged lines hidden --- | 166 167add 000010 ..... ..... .... 0110.. - ..... @rrr_cf_sh 168add_l 000010 ..... ..... .... 1010.. 0 ..... @rrr_cf_sh 169add_tsv 000010 ..... ..... .... 1110.. 0 ..... @rrr_cf_sh 170add_c 000010 ..... ..... .... 011100 0 ..... @rrr_cf_sh0 171add_c_tsv 000010 ..... ..... .... 111100 0 ..... @rrr_cf_sh0 172 173sub 000010 ..... ..... .... 010000 - ..... @rrr_cf --- 360 unchanged lines hidden --- |