| insns.decode (151f309b989fd84bec0cbd5bc84dbe83bbe0b2f4) | insns.decode (3bbb8e4832b56cea29a61eb32cfb4931e00244c1) |
|---|---|
| 1# 2# HPPA instruction decode definitions. 3# 4# Copyright (c) 2018 Richard Henderson <rth@twiddle.net> 5# 6# This library is free software; you can redistribute it and/or 7# modify it under the terms of the GNU Lesser General Public 8# License as published by the Free Software Foundation; either --- 54 unchanged lines hidden (view full) --- 63 64# All insns that need to form a virtual address should use this set. 65&ldst t b x disp sp m scale size 66 67&rr_cf_d t r cf d 68&rrr t r1 r2 69&rrr_cf t r1 r2 cf 70&rrr_cf_d t r1 r2 cf d | 1# 2# HPPA instruction decode definitions. 3# 4# Copyright (c) 2018 Richard Henderson <rth@twiddle.net> 5# 6# This library is free software; you can redistribute it and/or 7# modify it under the terms of the GNU Lesser General Public 8# License as published by the Free Software Foundation; either --- 54 unchanged lines hidden (view full) --- 63 64# All insns that need to form a virtual address should use this set. 65&ldst t b x disp sp m scale size 66 67&rr_cf_d t r cf d 68&rrr t r1 r2 69&rrr_cf t r1 r2 cf 70&rrr_cf_d t r1 r2 cf d |
| 71&rrr_sh t r1 r2 sh |
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| 71&rrr_cf_d_sh t r1 r2 cf d sh 72&rri t r i 73&rri_cf t r i cf 74&rri_cf_d t r i cf d 75 76&rrb_c_f disp n c f r1 r2 77&rrb_c_d_f disp n c d f r1 r2 78&rib_c_f disp n c f r i 79&rib_c_d_f disp n c d f r i 80 81#### 82# Format definitions 83#### 84 85@rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d 86@rrr ...... r2:5 r1:5 .... ....... t:5 &rrr 87@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf 88@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d | 72&rrr_cf_d_sh t r1 r2 cf d sh 73&rri t r i 74&rri_cf t r i cf 75&rri_cf_d t r i cf d 76 77&rrb_c_f disp n c f r1 r2 78&rrb_c_d_f disp n c d f r1 r2 79&rib_c_f disp n c f r i 80&rib_c_d_f disp n c d f r i 81 82#### 83# Format definitions 84#### 85 86@rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d 87@rrr ...... r2:5 r1:5 .... ....... t:5 &rrr 88@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf 89@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d |
| 90@rrr_sh ...... r2:5 r1:5 ........ sh:2 . t:5 &rrr_sh |
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| 89@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh 90@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d_sh sh=0 91@rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11 92@rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=%lowsign_11 93 94@rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \ 95 &rrb_c_f disp=%assemble_12 96@rrb_cdf ...... r2:5 r1:5 c:3 ........... n:1 . \ --- 85 unchanged lines hidden (view full) --- 182uaddcm 000010 ..... ..... .... 100110 . ..... @rrr_cf_d 183uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d 184dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d 185dcor_i 000010 ..... 00000 .... 101111 . ..... @rr_cf_d 186 187add 000010 ..... ..... .... 0110.. . ..... @rrr_cf_d_sh 188add_l 000010 ..... ..... .... 1010.. . ..... @rrr_cf_d_sh 189add_tsv 000010 ..... ..... .... 1110.. . ..... @rrr_cf_d_sh | 91@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh 92@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d_sh sh=0 93@rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11 94@rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=%lowsign_11 95 96@rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \ 97 &rrb_c_f disp=%assemble_12 98@rrb_cdf ...... r2:5 r1:5 c:3 ........... n:1 . \ --- 85 unchanged lines hidden (view full) --- 184uaddcm 000010 ..... ..... .... 100110 . ..... @rrr_cf_d 185uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d 186dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d 187dcor_i 000010 ..... 00000 .... 101111 . ..... @rr_cf_d 188 189add 000010 ..... ..... .... 0110.. . ..... @rrr_cf_d_sh 190add_l 000010 ..... ..... .... 1010.. . ..... @rrr_cf_d_sh 191add_tsv 000010 ..... ..... .... 1110.. . ..... @rrr_cf_d_sh |
| 190add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0 | 192{ 193 add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0 194 hshladd 000010 ..... ..... 0000 0111.. 0 ..... @rrr_sh 195} |
| 191add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0 192 193sub 000010 ..... ..... .... 010000 . ..... @rrr_cf_d 194sub_tsv 000010 ..... ..... .... 110000 . ..... @rrr_cf_d 195sub_tc 000010 ..... ..... .... 010011 . ..... @rrr_cf_d 196sub_tsv_tc 000010 ..... ..... .... 110011 . ..... @rrr_cf_d | 196add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0 197 198sub 000010 ..... ..... .... 010000 . ..... @rrr_cf_d 199sub_tsv 000010 ..... ..... .... 110000 . ..... @rrr_cf_d 200sub_tc 000010 ..... ..... .... 010011 . ..... @rrr_cf_d 201sub_tsv_tc 000010 ..... ..... .... 110011 . ..... @rrr_cf_d |
| 197sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d | 202{ 203 sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d 204 hshradd 000010 ..... ..... 0000 0101.. 0 ..... @rrr_sh 205} |
| 198sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d 199 200ldil 001000 t:5 ..................... i=%assemble_21 201addil 001010 r:5 ..................... i=%assemble_21 202ldo 001101 b:5 t:5 -- .............. i=%lowsign_14 203 204addi 101101 ..... ..... .... 0 ........... @rri_cf 205addi_tsv 101101 ..... ..... .... 1 ........... @rri_cf --- 388 unchanged lines hidden --- | 206sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d 207 208ldil 001000 t:5 ..................... i=%assemble_21 209addil 001010 r:5 ..................... i=%assemble_21 210ldo 001101 b:5 t:5 -- .............. i=%lowsign_14 211 212addi 101101 ..... ..... .... 0 ........... @rri_cf 213addi_tsv 101101 ..... ..... .... 1 ........... @rri_cf --- 388 unchanged lines hidden --- |