genptr.c (72895676e73c06a5c331777015b3780efda4edd0) genptr.c (d63aeb3b7ea770dac4ab13eb1e19a943a198a28d)
1/*
2 * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *

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38}
39
40TCGv gen_read_preg(TCGv pred, uint8_t num)
41{
42 tcg_gen_mov_tl(pred, hex_pred[num]);
43 return pred;
44}
45
1/*
2 * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *

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38}
39
40TCGv gen_read_preg(TCGv pred, uint8_t num)
41{
42 tcg_gen_mov_tl(pred, hex_pred[num]);
43 return pred;
44}
45
46#define IMMUTABLE (~0)
47
48static const target_ulong reg_immut_masks[TOTAL_PER_THREAD_REGS] = {
49 [HEX_REG_USR] = 0xc13000c0,
50 [HEX_REG_PC] = IMMUTABLE,
51 [HEX_REG_GP] = 0x3f,
52 [HEX_REG_UPCYCLELO] = IMMUTABLE,
53 [HEX_REG_UPCYCLEHI] = IMMUTABLE,
54 [HEX_REG_UTIMERLO] = IMMUTABLE,
55 [HEX_REG_UTIMERHI] = IMMUTABLE,
56};
57
58static inline void gen_masked_reg_write(TCGv new_val, TCGv cur_val,
59 target_ulong reg_mask)
60{
61 if (reg_mask) {
62 TCGv tmp = tcg_temp_new();
63
64 /* new_val = (new_val & ~reg_mask) | (cur_val & reg_mask) */
65 tcg_gen_andi_tl(new_val, new_val, ~reg_mask);
66 tcg_gen_andi_tl(tmp, cur_val, reg_mask);
67 tcg_gen_or_tl(new_val, new_val, tmp);
68
69 tcg_temp_free(tmp);
70 }
71}
72
46static inline void gen_log_predicated_reg_write(int rnum, TCGv val,
47 uint32_t slot)
48{
49 TCGv zero = tcg_constant_tl(0);
50 TCGv slot_mask = tcg_temp_new();
51
52 tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot);
53 tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero,

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64 tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
65 }
66
67 tcg_temp_free(slot_mask);
68}
69
70void gen_log_reg_write(int rnum, TCGv val)
71{
73static inline void gen_log_predicated_reg_write(int rnum, TCGv val,
74 uint32_t slot)
75{
76 TCGv zero = tcg_constant_tl(0);
77 TCGv slot_mask = tcg_temp_new();
78
79 tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot);
80 tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero,

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91 tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
92 }
93
94 tcg_temp_free(slot_mask);
95}
96
97void gen_log_reg_write(int rnum, TCGv val)
98{
99 const target_ulong reg_mask = reg_immut_masks[rnum];
100
101 gen_masked_reg_write(val, hex_gpr[rnum], reg_mask);
72 tcg_gen_mov_tl(hex_new_value[rnum], val);
73 if (HEX_DEBUG) {
74 /* Do this so HELPER(debug_commit_end) will know */
75 tcg_gen_movi_tl(hex_reg_written[rnum], 1);
76 }
77}
78
79static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val,

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109 }
110
111 tcg_temp_free(val32);
112 tcg_temp_free(slot_mask);
113}
114
115static void gen_log_reg_write_pair(int rnum, TCGv_i64 val)
116{
102 tcg_gen_mov_tl(hex_new_value[rnum], val);
103 if (HEX_DEBUG) {
104 /* Do this so HELPER(debug_commit_end) will know */
105 tcg_gen_movi_tl(hex_reg_written[rnum], 1);
106 }
107}
108
109static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val,

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139 }
140
141 tcg_temp_free(val32);
142 tcg_temp_free(slot_mask);
143}
144
145static void gen_log_reg_write_pair(int rnum, TCGv_i64 val)
146{
147 const target_ulong reg_mask_low = reg_immut_masks[rnum];
148 const target_ulong reg_mask_high = reg_immut_masks[rnum + 1];
149 TCGv val32 = tcg_temp_new();
150
117 /* Low word */
151 /* Low word */
118 tcg_gen_extrl_i64_i32(hex_new_value[rnum], val);
152 tcg_gen_extrl_i64_i32(val32, val);
153 gen_masked_reg_write(val32, hex_gpr[rnum], reg_mask_low);
154 tcg_gen_mov_tl(hex_new_value[rnum], val32);
119 if (HEX_DEBUG) {
120 /* Do this so HELPER(debug_commit_end) will know */
121 tcg_gen_movi_tl(hex_reg_written[rnum], 1);
122 }
123
124 /* High word */
155 if (HEX_DEBUG) {
156 /* Do this so HELPER(debug_commit_end) will know */
157 tcg_gen_movi_tl(hex_reg_written[rnum], 1);
158 }
159
160 /* High word */
125 tcg_gen_extrh_i64_i32(hex_new_value[rnum + 1], val);
161 tcg_gen_extrh_i64_i32(val32, val);
162 gen_masked_reg_write(val32, hex_gpr[rnum + 1], reg_mask_high);
163 tcg_gen_mov_tl(hex_new_value[rnum + 1], val32);
126 if (HEX_DEBUG) {
127 /* Do this so HELPER(debug_commit_end) will know */
128 tcg_gen_movi_tl(hex_reg_written[rnum + 1], 1);
129 }
164 if (HEX_DEBUG) {
165 /* Do this so HELPER(debug_commit_end) will know */
166 tcg_gen_movi_tl(hex_reg_written[rnum + 1], 1);
167 }
168
169 tcg_temp_free(val32);
130}
131
132void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val)
133{
134 TCGv base_val = tcg_temp_new();
135
136 tcg_gen_andi_tl(base_val, val, 0xff);
137

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171
172void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val)
173{
174 TCGv base_val = tcg_temp_new();
175
176 tcg_gen_andi_tl(base_val, val, 0xff);
177

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