translate.c (d53106c997e5c8e61e37ae9ff9f0e1f243b03968) | translate.c (e4eff8e4edc188b5eee8834479b515325889e27a) |
---|---|
1/* 2 * ARM translation 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2005-2007 CodeSourcery 6 * Copyright (c) 2007 OpenedHand, Ltd. 7 * 8 * This library is free software; you can redistribute it and/or --- 18 unchanged lines hidden (view full) --- 27#include "tcg/tcg-op.h" 28#include "tcg/tcg-op-gvec.h" 29#include "qemu/log.h" 30#include "qemu/bitops.h" 31#include "arm_ldst.h" 32#include "semihosting/semihost.h" 33#include "exec/log.h" 34#include "cpregs.h" | 1/* 2 * ARM translation 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2005-2007 CodeSourcery 6 * Copyright (c) 2007 OpenedHand, Ltd. 7 * 8 * This library is free software; you can redistribute it and/or --- 18 unchanged lines hidden (view full) --- 27#include "tcg/tcg-op.h" 28#include "tcg/tcg-op-gvec.h" 29#include "qemu/log.h" 30#include "qemu/bitops.h" 31#include "arm_ldst.h" 32#include "semihosting/semihost.h" 33#include "exec/log.h" 34#include "cpregs.h" |
35#include "translate.h" 36#include "translate-a32.h" 37#include "exec/gen-icount.h" |
|
35 36#define HELPER_H "helper.h" 37#include "exec/helper-info.c.inc" 38#undef HELPER_H 39 40#define ENABLE_ARCH_4T arm_dc_feature(s, ARM_FEATURE_V4T) 41#define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5) 42/* currently all emulated v5 cores are also v5TE, so don't bother */ 43#define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5) 44#define ENABLE_ARCH_5J dc_isar_feature(aa32_jazelle, s) 45#define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6) 46#define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K) 47#define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2) 48#define ENABLE_ARCH_7 arm_dc_feature(s, ARM_FEATURE_V7) 49#define ENABLE_ARCH_8 arm_dc_feature(s, ARM_FEATURE_V8) 50 | 38 39#define HELPER_H "helper.h" 40#include "exec/helper-info.c.inc" 41#undef HELPER_H 42 43#define ENABLE_ARCH_4T arm_dc_feature(s, ARM_FEATURE_V4T) 44#define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5) 45/* currently all emulated v5 cores are also v5TE, so don't bother */ 46#define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5) 47#define ENABLE_ARCH_5J dc_isar_feature(aa32_jazelle, s) 48#define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6) 49#define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K) 50#define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2) 51#define ENABLE_ARCH_7 arm_dc_feature(s, ARM_FEATURE_V7) 52#define ENABLE_ARCH_8 arm_dc_feature(s, ARM_FEATURE_V8) 53 |
51#include "translate.h" 52#include "translate-a32.h" 53 | |
54/* These are TCG temporaries used only by the legacy iwMMXt decoder */ 55static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; 56/* These are TCG globals which alias CPUARMState fields */ 57static TCGv_i32 cpu_R[16]; 58TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF; 59TCGv_i64 cpu_exclusive_addr; 60TCGv_i64 cpu_exclusive_val; 61 | 54/* These are TCG temporaries used only by the legacy iwMMXt decoder */ 55static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; 56/* These are TCG globals which alias CPUARMState fields */ 57static TCGv_i32 cpu_R[16]; 58TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF; 59TCGv_i64 cpu_exclusive_addr; 60TCGv_i64 cpu_exclusive_val; 61 |
62#include "exec/gen-icount.h" 63 | |
64static const char * const regnames[] = 65 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 66 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" }; 67 68 69/* initialize TCG globals. */ 70void arm_translate_init(void) 71{ --- 9653 unchanged lines hidden --- | 62static const char * const regnames[] = 63 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 64 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" }; 65 66 67/* initialize TCG globals. */ 68void arm_translate_init(void) 69{ --- 9653 unchanged lines hidden --- |