ptw.c (465af4db965322630b253691b569b40cf84a2dbc) ptw.c (6d03226b42247b68ab2f0b3663e0f624335a4055)
1/*
2 * ARM page table walking.
3 *
4 * This code is licensed under the GNU GPL v2 or later.
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8

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484 ptw->out_secure = s2.f.attrs.secure;
485 ptw->out_space = s2.f.attrs.space;
486 } else {
487#ifdef CONFIG_TCG
488 CPUTLBEntryFull *full;
489 int flags;
490
491 env->tlb_fi = fi;
1/*
2 * ARM page table walking.
3 *
4 * This code is licensed under the GNU GPL v2 or later.
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8

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484 ptw->out_secure = s2.f.attrs.secure;
485 ptw->out_space = s2.f.attrs.space;
486 } else {
487#ifdef CONFIG_TCG
488 CPUTLBEntryFull *full;
489 int flags;
490
491 env->tlb_fi = fi;
492 flags = probe_access_full(env, addr, 0, MMU_DATA_LOAD,
493 arm_to_core_mmu_idx(s2_mmu_idx),
494 true, &ptw->out_host, &full, 0);
492 flags = probe_access_full_mmu(env, addr, 0, MMU_DATA_LOAD,
493 arm_to_core_mmu_idx(s2_mmu_idx),
494 &ptw->out_host, &full);
495 env->tlb_fi = NULL;
496
497 if (unlikely(flags & TLB_INVALID_MASK)) {
498 goto fail;
499 }
500 ptw->out_phys = full->phys_addr | (addr & ~TARGET_PAGE_MASK);
501 ptw->out_rw = full->prot & PAGE_WRITE;
502 pte_attrs = full->pte_attrs;

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639 }
640
641 /*
642 * Raising a stage2 Protection fault for an atomic update to a read-only
643 * page is delayed until it is certain that there is a change to make.
644 */
645 if (unlikely(!ptw->out_rw)) {
646 int flags;
495 env->tlb_fi = NULL;
496
497 if (unlikely(flags & TLB_INVALID_MASK)) {
498 goto fail;
499 }
500 ptw->out_phys = full->phys_addr | (addr & ~TARGET_PAGE_MASK);
501 ptw->out_rw = full->prot & PAGE_WRITE;
502 pte_attrs = full->pte_attrs;

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639 }
640
641 /*
642 * Raising a stage2 Protection fault for an atomic update to a read-only
643 * page is delayed until it is certain that there is a change to make.
644 */
645 if (unlikely(!ptw->out_rw)) {
646 int flags;
647 void *discard;
648
649 env->tlb_fi = fi;
647
648 env->tlb_fi = fi;
650 flags = probe_access_flags(env, ptw->out_virt, 0, MMU_DATA_STORE,
651 arm_to_core_mmu_idx(ptw->in_ptw_idx),
652 true, &discard, 0);
649 flags = probe_access_full_mmu(env, ptw->out_virt, 0,
650 MMU_DATA_STORE,
651 arm_to_core_mmu_idx(ptw->in_ptw_idx),
652 NULL, NULL);
653 env->tlb_fi = NULL;
654
655 if (unlikely(flags & TLB_INVALID_MASK)) {
656 assert(fi->type != ARMFault_None);
657 fi->s2addr = ptw->out_virt;
658 fi->stage2 = true;
659 fi->s1ptw = true;
660 fi->s1ns = !ptw->in_secure;

--- 2743 unchanged lines hidden --- 		653 env->tlb_fi = NULL;
654
655 if (unlikely(flags & TLB_INVALID_MASK)) {
656 assert(fi->type != ARMFault_None);
657 fi->s2addr = ptw->out_virt;
658 fi->stage2 = true;
659 fi->s1ptw = true;
660 fi->s1ns = !ptw->in_secure;

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