internals.h (88ce6c6ee85d902f59dc65afc3ca86b34f02b9ed) internals.h (4426d3617d64922d97b74ed22e67e33b6fb7de0a)
1/*
2 * QEMU ARM CPU -- internal functions and types
3 *
4 * Copyright (c) 2014 Linaro Ltd
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2

--- 927 unchanged lines hidden (view full) ---

936 * Note that the ID register BRPS field is "number of bps - 1",
937 * and we return the actual number of breakpoints.
938 */
939static inline int arm_num_brps(ARMCPU *cpu)
940{
941 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
942 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1;
943 } else {
1/*
2 * QEMU ARM CPU -- internal functions and types
3 *
4 * Copyright (c) 2014 Linaro Ltd
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2

--- 927 unchanged lines hidden (view full) ---

936 * Note that the ID register BRPS field is "number of bps - 1",
937 * and we return the actual number of breakpoints.
938 */
939static inline int arm_num_brps(ARMCPU *cpu)
940{
941 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
942 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1;
943 } else {
944 return FIELD_EX32(cpu->dbgdidr, DBGDIDR, BRPS) + 1;
944 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1;
945 }
946}
947
948/**
949 * arm_num_wrps: Return number of implemented watchpoints.
950 * Note that the ID register WRPS field is "number of wps - 1",
951 * and we return the actual number of watchpoints.
952 */
953static inline int arm_num_wrps(ARMCPU *cpu)
954{
955 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
956 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1;
957 } else {
945 }
946}
947
948/**
949 * arm_num_wrps: Return number of implemented watchpoints.
950 * Note that the ID register WRPS field is "number of wps - 1",
951 * and we return the actual number of watchpoints.
952 */
953static inline int arm_num_wrps(ARMCPU *cpu)
954{
955 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
956 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1;
957 } else {
958 return FIELD_EX32(cpu->dbgdidr, DBGDIDR, WRPS) + 1;
958 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1;
959 }
960}
961
962/**
963 * arm_num_ctx_cmps: Return number of implemented context comparators.
964 * Note that the ID register CTX_CMPS field is "number of cmps - 1",
965 * and we return the actual number of comparators.
966 */
967static inline int arm_num_ctx_cmps(ARMCPU *cpu)
968{
969 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
970 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + 1;
971 } else {
959 }
960}
961
962/**
963 * arm_num_ctx_cmps: Return number of implemented context comparators.
964 * Note that the ID register CTX_CMPS field is "number of cmps - 1",
965 * and we return the actual number of comparators.
966 */
967static inline int arm_num_ctx_cmps(ARMCPU *cpu)
968{
969 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
970 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + 1;
971 } else {
972 return FIELD_EX32(cpu->dbgdidr, DBGDIDR, CTX_CMPS) + 1;
972 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1;
973 }
974}
975
976/* Note make_memop_idx reserves 4 bits for mmu_idx, and MO_BSWAP is bit 3.
977 * Thus a TCGMemOpIdx, without any MO_ALIGN bits, fits in 8 bits.
978 */
979#define MEMOPIDX_SHIFT 8
980

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974}
975
976/* Note make_memop_idx reserves 4 bits for mmu_idx, and MO_BSWAP is bit 3.
977 * Thus a TCGMemOpIdx, without any MO_ALIGN bits, fits in 8 bits.
978 */
979#define MEMOPIDX_SHIFT 8
980

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