| helper.c (9ac5df20f51fabcba0d902025df4bd7ea987c158) | helper.c (7fbc6a403a0aab834e764fa61d81ed8586cfe352) |
|---|---|
| 1/* 2 * ARM generic helpers. 3 * 4 * This code is licensed under the GNU GPL v2 or later. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 --- 880 unchanged lines hidden (view full) --- 889 uint32_t mask = 0; 890 891 /* In ARMv8 most bits of CPACR_EL1 are RES0. */ 892 if (!arm_feature(env, ARM_FEATURE_V8)) { 893 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. 894 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. 895 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. 896 */ | 1/* 2 * ARM generic helpers. 3 * 4 * This code is licensed under the GNU GPL v2 or later. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 --- 880 unchanged lines hidden (view full) --- 889 uint32_t mask = 0; 890 891 /* In ARMv8 most bits of CPACR_EL1 are RES0. */ 892 if (!arm_feature(env, ARM_FEATURE_V8)) { 893 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. 894 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. 895 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. 896 */ |
| 897 if (arm_feature(env, ARM_FEATURE_VFP)) { | 897 if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { |
| 898 /* VFP coprocessor: cp10 & cp11 [23:20] */ 899 mask |= (1 << 31) | (1 << 30) | (0xf << 20); 900 901 if (!arm_feature(env, ARM_FEATURE_NEON)) { 902 /* ASEDIS [31] bit is RAO/WI */ 903 value |= (1 << 31); 904 } 905 --- 6903 unchanged lines hidden (view full) --- 7809 aarch64_fpu_gdb_set_reg, 7810 34, "aarch64-fpu.xml", 0); 7811 } else if (arm_feature(env, ARM_FEATURE_NEON)) { 7812 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 7813 51, "arm-neon.xml", 0); 7814 } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { 7815 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 7816 35, "arm-vfp3.xml", 0); | 898 /* VFP coprocessor: cp10 & cp11 [23:20] */ 899 mask |= (1 << 31) | (1 << 30) | (0xf << 20); 900 901 if (!arm_feature(env, ARM_FEATURE_NEON)) { 902 /* ASEDIS [31] bit is RAO/WI */ 903 value |= (1 << 31); 904 } 905 --- 6903 unchanged lines hidden (view full) --- 7809 aarch64_fpu_gdb_set_reg, 7810 34, "aarch64-fpu.xml", 0); 7811 } else if (arm_feature(env, ARM_FEATURE_NEON)) { 7812 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 7813 51, "arm-neon.xml", 0); 7814 } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { 7815 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 7816 35, "arm-vfp3.xml", 0); |
| 7817 } else if (arm_feature(env, ARM_FEATURE_VFP)) { | 7817 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { |
| 7818 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 7819 19, "arm-vfp.xml", 0); 7820 } 7821 gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, 7822 arm_gen_dynamic_xml(cs), 7823 "system-registers.xml", 0); 7824} 7825 --- 4701 unchanged lines hidden --- | 7818 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 7819 19, "arm-vfp.xml", 0); 7820 } 7821 gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, 7822 arm_gen_dynamic_xml(cs), 7823 "system-registers.xml", 0); 7824} 7825 --- 4701 unchanged lines hidden --- |