helper.c (9861248f637ecf11113b04b0b5c7b13c9aa06f09) helper.c (926c1b97895879b78ca14bca2831c08740ed1c38)
1/*
2 * ARM generic helpers.
3 *
4 * This code is licensed under the GNU GPL v2 or later.
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8

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528static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
529 const ARMCPRegInfo *ri,
530 bool isread)
531{
532 if (arm_current_el(env) == 3) {
533 return CP_ACCESS_OK;
534 }
535 if (arm_is_secure_below_el3(env)) {
1/*
2 * ARM generic helpers.
3 *
4 * This code is licensed under the GNU GPL v2 or later.
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8

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528static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
529 const ARMCPRegInfo *ri,
530 bool isread)
531{
532 if (arm_current_el(env) == 3) {
533 return CP_ACCESS_OK;
534 }
535 if (arm_is_secure_below_el3(env)) {
536 if (env->cp15.scr_el3 & SCR_EEL2) {
537 return CP_ACCESS_TRAP_EL2;
538 }
536 return CP_ACCESS_TRAP_EL3;
537 }
538 /* This will be EL1 NS and EL2 NS, which just UNDEF */
539 return CP_ACCESS_TRAP_UNCATEGORIZED;
540}
541
542static uint64_t arm_mdcr_el2_eff(CPUARMState *env)
543{

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2025 valid_mask &= ~SCR_NET;
2026
2027 if (cpu_isar_feature(aa64_lor, cpu)) {
2028 valid_mask |= SCR_TLOR;
2029 }
2030 if (cpu_isar_feature(aa64_pauth, cpu)) {
2031 valid_mask |= SCR_API | SCR_APK;
2032 }
539 return CP_ACCESS_TRAP_EL3;
540 }
541 /* This will be EL1 NS and EL2 NS, which just UNDEF */
542 return CP_ACCESS_TRAP_UNCATEGORIZED;
543}
544
545static uint64_t arm_mdcr_el2_eff(CPUARMState *env)
546{

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2028 valid_mask &= ~SCR_NET;
2029
2030 if (cpu_isar_feature(aa64_lor, cpu)) {
2031 valid_mask |= SCR_TLOR;
2032 }
2033 if (cpu_isar_feature(aa64_pauth, cpu)) {
2034 valid_mask |= SCR_API | SCR_APK;
2035 }
2036 if (cpu_isar_feature(aa64_sel2, cpu)) {
2037 valid_mask |= SCR_EEL2;
2038 }
2033 if (cpu_isar_feature(aa64_mte, cpu)) {
2034 valid_mask |= SCR_ATA;
2035 }
2036 } else {
2037 valid_mask &= ~(SCR_RW | SCR_ST);
2038 }
2039
2040 if (!arm_feature(env, ARM_FEATURE_EL2)) {

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3383
3384#ifndef CONFIG_USER_ONLY
3385/* get_phys_addr() isn't present for user-mode-only targets */
3386
3387static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
3388 bool isread)
3389{
3390 if (ri->opc2 & 4) {
2039 if (cpu_isar_feature(aa64_mte, cpu)) {
2040 valid_mask |= SCR_ATA;
2041 }
2042 } else {
2043 valid_mask &= ~(SCR_RW | SCR_ST);
2044 }
2045
2046 if (!arm_feature(env, ARM_FEATURE_EL2)) {

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3389
3390#ifndef CONFIG_USER_ONLY
3391/* get_phys_addr() isn't present for user-mode-only targets */
3392
3393static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
3394 bool isread)
3395{
3396 if (ri->opc2 & 4) {
3391 /* The ATS12NSO* operations must trap to EL3 if executed in
3397 /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in
3392 * Secure EL1 (which can only happen if EL3 is AArch64).
3393 * They are simply UNDEF if executed from NS EL1.
3394 * They function normally from EL2 or EL3.
3395 */
3396 if (arm_current_el(env) == 1) {
3397 if (arm_is_secure_below_el3(env)) {
3398 * Secure EL1 (which can only happen if EL3 is AArch64).
3399 * They are simply UNDEF if executed from NS EL1.
3400 * They function normally from EL2 or EL3.
3401 */
3402 if (arm_current_el(env) == 1) {
3403 if (arm_is_secure_below_el3(env)) {
3404 if (env->cp15.scr_el3 & SCR_EEL2) {
3405 return CP_ACCESS_TRAP_UNCATEGORIZED_EL2;
3406 }
3398 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
3399 }
3400 return CP_ACCESS_TRAP_UNCATEGORIZED;
3401 }
3402 }
3403 return CP_ACCESS_OK;
3404}
3405

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3652 /* Handled by hardware accelerator. */
3653 g_assert_not_reached();
3654#endif /* CONFIG_TCG */
3655}
3656
3657static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
3658 bool isread)
3659{
3407 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
3408 }
3409 return CP_ACCESS_TRAP_UNCATEGORIZED;
3410 }
3411 }
3412 return CP_ACCESS_OK;
3413}
3414

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3661 /* Handled by hardware accelerator. */
3662 g_assert_not_reached();
3663#endif /* CONFIG_TCG */
3664}
3665
3666static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
3667 bool isread)
3668{
3660 if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
3669 if (arm_current_el(env) == 3 &&
3670 !(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) {
3661 return CP_ACCESS_TRAP;
3662 }
3663 return CP_ACCESS_OK;
3664}
3665
3666static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
3667 uint64_t value)
3668{

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5751 .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) },
5752 REGINFO_SENTINEL
5753};
5754
5755static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
5756 bool isread)
5757{
5758 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
3671 return CP_ACCESS_TRAP;
3672 }
3673 return CP_ACCESS_OK;
3674}
3675
3676static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
3677 uint64_t value)
3678{

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5761 .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) },
5762 REGINFO_SENTINEL
5763};
5764
5765static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
5766 bool isread)
5767{
5768 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
5759 * At Secure EL1 it traps to EL3.
5769 * At Secure EL1 it traps to EL3 or EL2.
5760 */
5761 if (arm_current_el(env) == 3) {
5762 return CP_ACCESS_OK;
5763 }
5764 if (arm_is_secure_below_el3(env)) {
5770 */
5771 if (arm_current_el(env) == 3) {
5772 return CP_ACCESS_OK;
5773 }
5774 if (arm_is_secure_below_el3(env)) {
5775 if (env->cp15.scr_el3 & SCR_EEL2) {
5776 return CP_ACCESS_TRAP_EL2;
5777 }
5765 return CP_ACCESS_TRAP_EL3;
5766 }
5767 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
5768 if (isread) {
5769 return CP_ACCESS_OK;
5770 }
5771 return CP_ACCESS_TRAP_UNCATEGORIZED;
5772}

--- 7554 unchanged lines hidden --- 		5778 return CP_ACCESS_TRAP_EL3;
5779 }
5780 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
5781 if (isread) {
5782 return CP_ACCESS_OK;
5783 }
5784 return CP_ACCESS_TRAP_UNCATEGORIZED;
5785}

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