debug_helper.c (266ccbb27b3ec6661f22395ec2c41d854c94d761) debug_helper.c (f9ac778898cb28307e0f91421aba34d43c34b679)
1/*
2 * ARM debug helpers.
3 *
4 * This code is licensed under the GNU GPL v2 or later.
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8#include "qemu/osdep.h"

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837 return CP_ACCESS_OK;
838}
839
840/*
841 * Check for traps to Debug Comms Channel registers. If FEAT_FGT
842 * is implemented then these are controlled by MDCR_EL2.TDCC for
843 * EL2 and MDCR_EL3.TDCC for EL3. They are also controlled by
844 * the general debug access trap bits MDCR_EL2.TDA and MDCR_EL3.TDA.
1/*
2 * ARM debug helpers.
3 *
4 * This code is licensed under the GNU GPL v2 or later.
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8#include "qemu/osdep.h"

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837 return CP_ACCESS_OK;
838}
839
840/*
841 * Check for traps to Debug Comms Channel registers. If FEAT_FGT
842 * is implemented then these are controlled by MDCR_EL2.TDCC for
843 * EL2 and MDCR_EL3.TDCC for EL3. They are also controlled by
844 * the general debug access trap bits MDCR_EL2.TDA and MDCR_EL3.TDA.
845 * For EL0, they are also controlled by MDSCR_EL1.TDCC.
845 */
846static CPAccessResult access_tdcc(CPUARMState *env, const ARMCPRegInfo *ri,
847 bool isread)
848{
849 int el = arm_current_el(env);
850 uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
846 */
847static CPAccessResult access_tdcc(CPUARMState *env, const ARMCPRegInfo *ri,
848 bool isread)
849{
850 int el = arm_current_el(env);
851 uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
852 bool mdscr_el1_tdcc = extract32(env->cp15.mdscr_el1, 12, 1);
851 bool mdcr_el2_tda = (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) ||
852 (arm_hcr_el2_eff(env) & HCR_TGE);
853 bool mdcr_el2_tdcc = cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
854 (mdcr_el2 & MDCR_TDCC);
855 bool mdcr_el3_tdcc = cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
856 (env->cp15.mdcr_el3 & MDCR_TDCC);
857
853 bool mdcr_el2_tda = (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) ||
854 (arm_hcr_el2_eff(env) & HCR_TGE);
855 bool mdcr_el2_tdcc = cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
856 (mdcr_el2 & MDCR_TDCC);
857 bool mdcr_el3_tdcc = cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
858 (env->cp15.mdcr_el3 & MDCR_TDCC);
859
860 if (el < 1 && mdscr_el1_tdcc) {
861 return CP_ACCESS_TRAP;
862 }
858 if (el < 2 && (mdcr_el2_tda || mdcr_el2_tdcc)) {
859 return CP_ACCESS_TRAP_EL2;
860 }
861 if (el < 3 && ((env->cp15.mdcr_el3 & MDCR_TDA) || mdcr_el3_tdcc)) {
862 return CP_ACCESS_TRAP_EL3;
863 }
864 return CP_ACCESS_OK;
865}

--- 383 unchanged lines hidden --- 		863 if (el < 2 && (mdcr_el2_tda || mdcr_el2_tdcc)) {
864 return CP_ACCESS_TRAP_EL2;
865 }
866 if (el < 3 && ((env->cp15.mdcr_el3 & MDCR_TDA) || mdcr_el3_tdcc)) {
867 return CP_ACCESS_TRAP_EL3;
868 }
869 return CP_ACCESS_OK;
870}

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