cpu64.c (f8e1d8852e393b3fd524fb005e38590063d99bc0) cpu64.c (eb94284d0812b4e7c11c5d075b584100ac1c1b9a)
1/*
2 * QEMU AArch64 CPU
3 *
4 * Copyright (c) 2013 Linaro Ltd
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2

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23#include "cpu.h"
24#include "qemu/module.h"
25#if !defined(CONFIG_USER_ONLY)
26#include "hw/loader.h"
27#endif
28#include "sysemu/kvm.h"
29#include "kvm_arm.h"
30#include "qapi/visitor.h"
1/*
2 * QEMU AArch64 CPU
3 *
4 * Copyright (c) 2013 Linaro Ltd
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2

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23#include "cpu.h"
24#include "qemu/module.h"
25#if !defined(CONFIG_USER_ONLY)
26#include "hw/loader.h"
27#endif
28#include "sysemu/kvm.h"
29#include "kvm_arm.h"
30#include "qapi/visitor.h"
31#include "hw/qdev-properties.h"
31
32
33
32#ifndef CONFIG_USER_ONLY
33static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
34{
35 ARMCPU *cpu = env_archcpu(env);
36
37 /* Number of cores is in [25:24]; otherwise we RAZ */
38 return (cpu->core_count - 1) << 24;
39}

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567 for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
568 char name[8];
569 sprintf(name, "sve%d", vq * 128);
570 object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
571 cpu_arm_set_sve_vq, NULL, NULL);
572 }
573}
574
34#ifndef CONFIG_USER_ONLY
35static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
36{
37 ARMCPU *cpu = env_archcpu(env);
38
39 /* Number of cores is in [25:24]; otherwise we RAZ */
40 return (cpu->core_count - 1) << 24;
41}

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569 for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
570 char name[8];
571 sprintf(name, "sve%d", vq * 128);
572 object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
573 cpu_arm_set_sve_vq, NULL, NULL);
574 }
575}
576
577void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
578{
579 int arch_val = 0, impdef_val = 0;
580 uint64_t t;
581
582 /* TODO: Handle HaveEnhancedPAC, HaveEnhancedPAC2, HaveFPAC. */
583 if (cpu->prop_pauth) {
584 if (cpu->prop_pauth_impdef) {
585 impdef_val = 1;
586 } else {
587 arch_val = 1;
588 }
589 } else if (cpu->prop_pauth_impdef) {
590 error_setg(errp, "cannot enable pauth-impdef without pauth");
591 error_append_hint(errp, "Add pauth=on to the CPU property list.\n");
592 }
593
594 t = cpu->isar.id_aa64isar1;
595 t = FIELD_DP64(t, ID_AA64ISAR1, APA, arch_val);
596 t = FIELD_DP64(t, ID_AA64ISAR1, GPA, arch_val);
597 t = FIELD_DP64(t, ID_AA64ISAR1, API, impdef_val);
598 t = FIELD_DP64(t, ID_AA64ISAR1, GPI, impdef_val);
599 cpu->isar.id_aa64isar1 = t;
600}
601
602static Property arm_cpu_pauth_property =
603 DEFINE_PROP_BOOL("pauth", ARMCPU, prop_pauth, true);
604static Property arm_cpu_pauth_impdef_property =
605 DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false);
606
575/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
576 * otherwise, a CPU with as many features enabled as our emulation supports.
577 * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
578 * this only needs to handle 64 bits.
579 */
580static void aarch64_max_initfn(Object *obj)
581{
582 ARMCPU *cpu = ARM_CPU(obj);

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622 t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
623 t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
624 cpu->isar.id_aa64isar0 = t;
625
626 t = cpu->isar.id_aa64isar1;
627 t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
628 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
629 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
607/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
608 * otherwise, a CPU with as many features enabled as our emulation supports.
609 * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
610 * this only needs to handle 64 bits.
611 */
612static void aarch64_max_initfn(Object *obj)
613{
614 ARMCPU *cpu = ARM_CPU(obj);

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654 t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
655 t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
656 cpu->isar.id_aa64isar0 = t;
657
658 t = cpu->isar.id_aa64isar1;
659 t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
660 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
661 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
630 t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */
631 t = FIELD_DP64(t, ID_AA64ISAR1, API, 0);
632 t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1);
633 t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0);
634 t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
635 t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
636 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
637 t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
638 cpu->isar.id_aa64isar1 = t;
639
640 t = cpu->isar.id_aa64pfr0;
641 t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);

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716
717#ifdef CONFIG_USER_ONLY
718 /* For usermode -cpu max we can use a larger and more efficient DCZ
719 * blocksize since we don't have to follow what the hardware does.
720 */
721 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
722 cpu->dcz_blocksize = 7; /* 512 bytes */
723#endif
662 t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
663 t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
664 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
665 t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
666 cpu->isar.id_aa64isar1 = t;
667
668 t = cpu->isar.id_aa64pfr0;
669 t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);

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744
745#ifdef CONFIG_USER_ONLY
746 /* For usermode -cpu max we can use a larger and more efficient DCZ
747 * blocksize since we don't have to follow what the hardware does.
748 */
749 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
750 cpu->dcz_blocksize = 7; /* 512 bytes */
751#endif
752
753 /* Default to PAUTH on, with the architected algorithm. */
754 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property);
755 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property);
724 }
725
726 aarch64_add_sve_properties(obj);
727 object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
728 cpu_max_set_sve_max_vq, NULL, NULL);
729}
730
731static const ARMCPUInfo aarch64_cpus[] = {

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757
758 aarch64_add_sve_properties(obj);
759 object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
760 cpu_max_set_sve_max_vq, NULL, NULL);
761}
762
763static const ARMCPUInfo aarch64_cpus[] = {

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