cpu64.c - OpenGrok cross reference for /openbmc/qemu/target/arm/cpu64.c

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cpu64.c (47576b94af5c406fc6521fb336fb5c12beeac3f8)	cpu64.c (962fcbf2efe57231a9f5df0ae0f40c05e35628ba)
1/* 2 * QEMU AArch64 CPU 3 * 4 * Copyright (c) 2013 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 --- 95 unchanged lines hidden (view full) --- 104 105 cpu->dtb_compatible = "arm,cortex-a57"; 106 set_feature(&cpu->env, ARM_FEATURE_V8); 107 set_feature(&cpu->env, ARM_FEATURE_VFP4); 108 set_feature(&cpu->env, ARM_FEATURE_NEON); 109 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 110 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 111 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);	1/* 2 * QEMU AArch64 CPU 3 * 4 * Copyright (c) 2013 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 --- 95 unchanged lines hidden (view full) --- 104 105 cpu->dtb_compatible = "arm,cortex-a57"; 106 set_feature(&cpu->env, ARM_FEATURE_V8); 107 set_feature(&cpu->env, ARM_FEATURE_VFP4); 108 set_feature(&cpu->env, ARM_FEATURE_NEON); 109 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 110 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 111 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
112 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 113 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 114 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 115 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 116 set_feature(&cpu->env, ARM_FEATURE_CRC);
117 set_feature(&cpu->env, ARM_FEATURE_EL2); 118 set_feature(&cpu->env, ARM_FEATURE_EL3); 119 set_feature(&cpu->env, ARM_FEATURE_PMU); 120 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; 121 cpu->midr = 0x411fd070; 122 cpu->revidr = 0x00000000; 123 cpu->reset_fpsid = 0x41034070; 124 cpu->isar.mvfr0 = 0x10110222; --- 40 unchanged lines hidden (view full) --- 165 166 cpu->dtb_compatible = "arm,cortex-a53"; 167 set_feature(&cpu->env, ARM_FEATURE_V8); 168 set_feature(&cpu->env, ARM_FEATURE_VFP4); 169 set_feature(&cpu->env, ARM_FEATURE_NEON); 170 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 171 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 172 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);	112 set_feature(&cpu->env, ARM_FEATURE_EL2); 113 set_feature(&cpu->env, ARM_FEATURE_EL3); 114 set_feature(&cpu->env, ARM_FEATURE_PMU); 115 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; 116 cpu->midr = 0x411fd070; 117 cpu->revidr = 0x00000000; 118 cpu->reset_fpsid = 0x41034070; 119 cpu->isar.mvfr0 = 0x10110222; --- 40 unchanged lines hidden (view full) --- 160 161 cpu->dtb_compatible = "arm,cortex-a53"; 162 set_feature(&cpu->env, ARM_FEATURE_V8); 163 set_feature(&cpu->env, ARM_FEATURE_VFP4); 164 set_feature(&cpu->env, ARM_FEATURE_NEON); 165 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 166 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 167 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
173 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 174 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 175 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 176 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 177 set_feature(&cpu->env, ARM_FEATURE_CRC);
178 set_feature(&cpu->env, ARM_FEATURE_EL2); 179 set_feature(&cpu->env, ARM_FEATURE_EL3); 180 set_feature(&cpu->env, ARM_FEATURE_PMU); 181 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; 182 cpu->midr = 0x410fd034; 183 cpu->revidr = 0x00000000; 184 cpu->reset_fpsid = 0x41034070; 185 cpu->isar.mvfr0 = 0x10110222; --- 38 unchanged lines hidden (view full) --- 224 225 cpu->dtb_compatible = "arm,cortex-a72"; 226 set_feature(&cpu->env, ARM_FEATURE_V8); 227 set_feature(&cpu->env, ARM_FEATURE_VFP4); 228 set_feature(&cpu->env, ARM_FEATURE_NEON); 229 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 230 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 231 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);	168 set_feature(&cpu->env, ARM_FEATURE_EL2); 169 set_feature(&cpu->env, ARM_FEATURE_EL3); 170 set_feature(&cpu->env, ARM_FEATURE_PMU); 171 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; 172 cpu->midr = 0x410fd034; 173 cpu->revidr = 0x00000000; 174 cpu->reset_fpsid = 0x41034070; 175 cpu->isar.mvfr0 = 0x10110222; --- 38 unchanged lines hidden (view full) --- 214 215 cpu->dtb_compatible = "arm,cortex-a72"; 216 set_feature(&cpu->env, ARM_FEATURE_V8); 217 set_feature(&cpu->env, ARM_FEATURE_VFP4); 218 set_feature(&cpu->env, ARM_FEATURE_NEON); 219 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 220 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 221 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
232 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 233 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 234 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 235 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 236 set_feature(&cpu->env, ARM_FEATURE_CRC);
237 set_feature(&cpu->env, ARM_FEATURE_EL2); 238 set_feature(&cpu->env, ARM_FEATURE_EL3); 239 set_feature(&cpu->env, ARM_FEATURE_PMU); 240 cpu->midr = 0x410fd083; 241 cpu->revidr = 0x00000000; 242 cpu->reset_fpsid = 0x41034080; 243 cpu->isar.mvfr0 = 0x10110222; 244 cpu->isar.mvfr1 = 0x12111111; --- 62 unchanged lines hidden (view full) --- 307 / 308static void aarch64_max_initfn(Object obj) 309{ 310 ARMCPU *cpu = ARM_CPU(obj); 311 312 if (kvm_enabled()) { 313 kvm_arm_set_cpu_features_from_host(cpu); 314 } else {	222 set_feature(&cpu->env, ARM_FEATURE_EL2); 223 set_feature(&cpu->env, ARM_FEATURE_EL3); 224 set_feature(&cpu->env, ARM_FEATURE_PMU); 225 cpu->midr = 0x410fd083; 226 cpu->revidr = 0x00000000; 227 cpu->reset_fpsid = 0x41034080; 228 cpu->isar.mvfr0 = 0x10110222; 229 cpu->isar.mvfr1 = 0x12111111; --- 62 unchanged lines hidden (view full) --- 292 / 293static void aarch64_max_initfn(Object obj) 294{ 295 ARMCPU *cpu = ARM_CPU(obj); 296 297 if (kvm_enabled()) { 298 kvm_arm_set_cpu_features_from_host(cpu); 299 } else {
	300 uint64_t t; 301 uint32_t u;
315 aarch64_a57_initfn(obj);	302 aarch64_a57_initfn(obj);
	303 304 t = cpu->isar.id_aa64isar0; 305 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL / 306 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); 307 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); / SHA512 / 308 t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); 309 t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); 310 t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); 311 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); 312 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); 313 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); 314 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); 315 cpu->isar.id_aa64isar0 = t; 316 317 t = cpu->isar.id_aa64isar1; 318 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); 319 cpu->isar.id_aa64isar1 = t; 320 321 / Replicate the same data to the 32-bit id registers. / 322 u = cpu->isar.id_isar5; 323 u = FIELD_DP32(u, ID_ISAR5, AES, 2); / AES + PMULL */ 324 u = FIELD_DP32(u, ID_ISAR5, SHA1, 1); 325 u = FIELD_DP32(u, ID_ISAR5, SHA2, 1); 326 u = FIELD_DP32(u, ID_ISAR5, CRC32, 1); 327 u = FIELD_DP32(u, ID_ISAR5, RDM, 1); 328 u = FIELD_DP32(u, ID_ISAR5, VCMA, 1); 329 cpu->isar.id_isar5 = u; 330 331 u = cpu->isar.id_isar6; 332 u = FIELD_DP32(u, ID_ISAR6, DP, 1); 333 cpu->isar.id_isar6 = u; 334
316#ifdef CONFIG_USER_ONLY 317 /* We don't set these in system emulation mode for the moment, 318 * since we don't correctly set the ID registers to advertise them, 319 * and in some cases they're only available in AArch64 and not AArch32, 320 * whereas the architecture requires them to be present in both if 321 * present in either. 322 */	335#ifdef CONFIG_USER_ONLY 336 /* We don't set these in system emulation mode for the moment, 337 * since we don't correctly set the ID registers to advertise them, 338 * and in some cases they're only available in AArch64 and not AArch32, 339 * whereas the architecture requires them to be present in both if 340 * present in either. 341 */
323 set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); 324 set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); 325 set_feature(&cpu->env, ARM_FEATURE_V8_SM3); 326 set_feature(&cpu->env, ARM_FEATURE_V8_SM4); 327 set_feature(&cpu->env, ARM_FEATURE_V8_ATOMICS); 328 set_feature(&cpu->env, ARM_FEATURE_V8_RDM); 329 set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD);
330 set_feature(&cpu->env, ARM_FEATURE_V8_FP16);	342 set_feature(&cpu->env, ARM_FEATURE_V8_FP16);
331 set_feature(&cpu->env, ARM_FEATURE_V8_FCMA);
332 set_feature(&cpu->env, ARM_FEATURE_SVE); 333 /* For usermode -cpu max we can use a larger and more efficient DCZ 334 * blocksize since we don't have to follow what the hardware does. 335 / 336 cpu->ctr = 0x80038003; / 32 byte I and D cacheline size, VIPT icache / 337 cpu->dcz_blocksize = 7; / 512 bytes / 338#endif 339 --- 133 unchanged lines hidden* ---	343 set_feature(&cpu->env, ARM_FEATURE_SVE); 344 /* For usermode -cpu max we can use a larger and more efficient DCZ 345 * blocksize since we don't have to follow what the hardware does. 346 / 347 cpu->ctr = 0x80038003; / 32 byte I and D cacheline size, VIPT icache / 348 cpu->dcz_blocksize = 7; / 512 bytes / 349#endif 350 --- 133 unchanged lines hidden* ---