cpu.h (d780d056f8acdee73a1c34d95733851d58aecd60) cpu.h (f4f318b41abe76a68ec1d616744ab9d6ec839abc)
1/*
2 * ARM virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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22
23#include "kvm-consts.h"
24#include "qemu/cpu-float.h"
25#include "hw/registerfields.h"
26#include "cpu-qom.h"
27#include "exec/cpu-defs.h"
28#include "qapi/qapi-types-common.h"
29#include "target/arm/multiprocessing.h"
1/*
2 * ARM virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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22
23#include "kvm-consts.h"
24#include "qemu/cpu-float.h"
25#include "hw/registerfields.h"
26#include "cpu-qom.h"
27#include "exec/cpu-defs.h"
28#include "qapi/qapi-types-common.h"
29#include "target/arm/multiprocessing.h"
30#include "target/arm/gtimer.h"
30
31/* ARM processors have a weak memory model */
32#define TCG_GUEST_DEFAULT_MO (0)
33
34#ifdef TARGET_AARCH64
35#define KVM_HAVE_MCE_INJECTION 1
36#endif
37

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135} DynamicGDBXMLInfo;
136
137/* CPU state for each instance of a generic timer (in cp15 c14) */
138typedef struct ARMGenericTimer {
139 uint64_t cval; /* Timer CompareValue register */
140 uint64_t ctl; /* Timer Control register */
141} ARMGenericTimer;
142
31
32/* ARM processors have a weak memory model */
33#define TCG_GUEST_DEFAULT_MO (0)
34
35#ifdef TARGET_AARCH64
36#define KVM_HAVE_MCE_INJECTION 1
37#endif
38

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136} DynamicGDBXMLInfo;
137
138/* CPU state for each instance of a generic timer (in cp15 c14) */
139typedef struct ARMGenericTimer {
140 uint64_t cval; /* Timer CompareValue register */
141 uint64_t ctl; /* Timer Control register */
142} ARMGenericTimer;
143
143#define GTIMER_PHYS 0
144#define GTIMER_VIRT 1
145#define GTIMER_HYP 2
146#define GTIMER_SEC 3
147#define GTIMER_HYPVIRT 4
148#define NUM_GTIMERS 5
149
150#define VTCR_NSW (1u << 29)
151#define VTCR_NSA (1u << 30)
152#define VSTCR_SW VTCR_NSW
153#define VSTCR_SA VTCR_NSA
154
155/* Define a maximum sized vector register.
156 * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
157 * For 64-bit, this is a 2048-bit SVE register.

--- 3280 unchanged lines hidden --- 		144#define VTCR_NSW (1u << 29)
145#define VTCR_NSA (1u << 30)
146#define VSTCR_SW VTCR_NSW
147#define VSTCR_SA VTCR_NSA
148
149/* Define a maximum sized vector register.
150 * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
151 * For 64-bit, this is a 2048-bit SVE register.

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