cpu.h (9ac5df20f51fabcba0d902025df4bd7ea987c158) cpu.h (7fbc6a403a0aab834e764fa61d81ed8586cfe352)
1/*
2 * ARM virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

--- 3436 unchanged lines hidden (view full) ---

3445 /*
3446 * This is a placeholder for use by VCMA until the rest of
3447 * the ARMv8.2-FP16 extension is implemented for aa32 mode.
3448 * At which point we can properly set and check MVFR1.FPHP.
3449 */
3450 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
3451}
3452
1/*
2 * ARM virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

--- 3436 unchanged lines hidden (view full) ---

3445 /*
3446 * This is a placeholder for use by VCMA until the rest of
3447 * the ARMv8.2-FP16 extension is implemented for aa32 mode.
3448 * At which point we can properly set and check MVFR1.FPHP.
3449 */
3450 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
3451}
3452
3453static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
3454{
3455 /*
3456 * Return true if either VFP or SIMD is implemented.
3457 * In this case, a minimum of VFP w/ D0-D15.
3458 */
3459 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;
3460}
3461
3453static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
3454{
3455 /* Return true if D16-D31 are implemented */
3456 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;
3457}
3458
3459static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
3460{

--- 299 unchanged lines hidden --- 		3462static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
3463{
3464 /* Return true if D16-D31 are implemented */
3465 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;
3466}
3467
3468static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
3469{

--- 299 unchanged lines hidden ---