cpu.h (9861248f637ecf11113b04b0b5c7b13c9aa06f09) cpu.h (926c1b97895879b78ca14bca2831c08740ed1c38)
1/*
2 * ARM virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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2159
2160/*
2161 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp.
2162 * This corresponds to the pseudocode EL2Enabled()
2163 */
2164static inline bool arm_is_el2_enabled(CPUARMState *env)
2165{
2166 if (arm_feature(env, ARM_FEATURE_EL2)) {
1/*
2 * ARM virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

--- 2150 unchanged lines hidden (view full) ---

2159
2160/*
2161 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp.
2162 * This corresponds to the pseudocode EL2Enabled()
2163 */
2164static inline bool arm_is_el2_enabled(CPUARMState *env)
2165{
2166 if (arm_feature(env, ARM_FEATURE_EL2)) {
2167 return !arm_is_secure_below_el3(env);
2167 if (arm_is_secure_below_el3(env)) {
2168 return (env->cp15.scr_el3 & SCR_EEL2) != 0;
2169 }
2170 return true;
2168 }
2169 return false;
2170}
2171
2172#else
2173static inline bool arm_is_secure_below_el3(CPUARMState *env)
2174{
2175 return false;

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2206 /* The highest exception level is always at the maximum supported
2207 * register width, and then lower levels have a register width controlled
2208 * by bits in the SCR or HCR registers.
2209 */
2210 if (el == 3) {
2211 return aa64;
2212 }
2213
2171 }
2172 return false;
2173}
2174
2175#else
2176static inline bool arm_is_secure_below_el3(CPUARMState *env)
2177{
2178 return false;

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2209 /* The highest exception level is always at the maximum supported
2210 * register width, and then lower levels have a register width controlled
2211 * by bits in the SCR or HCR registers.
2212 */
2213 if (el == 3) {
2214 return aa64;
2215 }
2216
2214 if (arm_feature(env, ARM_FEATURE_EL3)) {
2217 if (arm_feature(env, ARM_FEATURE_EL3) &&
2218 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) {
2215 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
2216 }
2217
2218 if (el == 2) {
2219 return aa64;
2220 }
2221
2222 if (arm_is_el2_enabled(env)) {

--- 1935 unchanged lines hidden --- 		2219 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
2220 }
2221
2222 if (el == 2) {
2223 return aa64;
2224 }
2225
2226 if (arm_is_el2_enabled(env)) {

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